Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3023526

1

T1

1

T3

11558

T6

1

auto[1]

15333

1

T3

174

T24

37

T32

4

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1005185

1

T1

1

T3

84

T6

1

auto[1]

2033674

1

T3

11648

T12

4306

T23

5998

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	605892	1			T1	1		T3	5567		T6	1
auto[524288:1048575]	386416	1			T3	983		T14	21		T16	112
auto[1048576:1572863]	385315	1			T14	1242		T16	329		T74	698
auto[1572864:2097151]	350103	1			T3	733		T14	1074		T74	2
auto[2097152:2621439]	303193	1			T3	3039		T14	500		T16	168
auto[2621440:3145727]	344107	1			T14	4713		T16	181		T74	233
auto[3145728:3670015]	350316	1			T3	167		T14	6360		T16	1
auto[3670016:4194303]	313517	1			T3	1243		T14	3753		T16	121

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2054447

1

T1

1

T3

11715

T6

1

auto[1]

984412

1

T3

17

T14

16964

T16

1200

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2629124

1

T1

1

T3

10391

T6

1

auto[1]

409735

1

T3

1341

T74

1830

T47

55

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	214312	1			T1	1		T3	11		T6	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	320699	1			T3	4799		T12	4306		T23	5998
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	131260	1			T3	5		T14	21		T16	112
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	199047	1			T3	949		T47	268		T35	5411
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	129105	1			T14	1242		T16	329		T74	238
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	186474	1			T47	1		T35	120		T73	772
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	126016	1			T3	8		T14	1074		T38	14501
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	171026	1			T3	521		T35	258		T59	2365
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	91535	1			T3	5		T14	500		T16	168
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	174176	1			T3	2648		T32	1		T47	514
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	96279	1			T14	4713		T16	181		T74	233
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	206680	1			T47	1088		T35	9		T60	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	112325	1			T3	9		T14	6360		T16	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	186628	1			T3	133		T35	788		T60	3114
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	94738	1			T3	9		T14	3753		T16	121
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	176171	1			T3	1192		T47	1		T35	258
auto[0]	auto[1]	auto[0:524287]	auto[0]	829	1			T3	2		T74	463		T47	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	67505	1			T3	731		T47	41		T35	1024
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2570	1			T47	5		T60	2		T103	1807
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	51843	1			T33	776		T90	128		T170	512
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1571	1			T74	460		T35	2		T103	434
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	66470	1			T35	1001		T73	258		T34	2891
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	705	1			T3	11		T74	2		T47	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	50687	1			T3	136		T60	1		T33	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	987	1			T3	2		T74	431		T33	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	34885	1			T3	384		T33	1407		T34	367
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	225	1			T102	19		T104	3		T41	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	39087	1			T41	1		T92	1250		T55	4207
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	782	1			T3	2		T74	474		T47	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	48376	1			T3	1		T47	3		T35	5207
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	209	1			T47	2		T35	1		T60	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	40324	1			T90	513		T41	2987		T44	512
auto[1]	auto[0]	auto[0:524287]	auto[0]	212	1			T3	1		T24	2		T32	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	1917	1			T24	35		T32	1		T35	5
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	175	1			T3	3		T47	1		T35	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1271	1			T3	26		T47	15		T35	45
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	158	1			T47	1		T34	2		T90	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1282	1			T47	17		T34	5		T90	29
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	181	1			T3	3		T35	2		T60	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1181	1			T3	20		T35	7		T60	25
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	173	1			T32	1		T47	1		T35	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	981	1			T32	1		T47	4		T35	16
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	162	1			T47	2		T87	1		T90	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1284	1			T47	51		T87	19		T90	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	147	1			T3	2		T35	11		T33	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1718	1			T3	5		T35	177		T33	34
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	199	1			T3	4		T47	1		T35	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1612	1			T3	38		T47	2		T35	6
auto[1]	auto[1]	auto[0:524287]	auto[0]	50	1			T3	1		T34	1		T90	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	368	1			T3	22		T34	2		T90	9
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	36	1			T33	1		T174	1		T45	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	214	1			T33	4		T174	19		T45	19
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	34	1			T92	1		T70	1		T139	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	221	1			T92	3		T70	6		T139	9
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	45	1			T3	5		T33	1		T174	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	262	1			T3	29		T33	1		T174	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	39	1			T33	1		T41	2		T46	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	417	1			T33	3		T41	15		T46	24
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	50	1			T41	1		T55	1		T44	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	340	1			T41	7		T55	13		T46	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	42	1			T3	1		T35	1		T41	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	298	1			T3	14		T35	3		T41	45
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	34	1			T90	1		T193	1		T139	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	230	1			T90	4		T139	22		T277	3

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1638416	1			T1	1		T3	10283		T6	1
auto[0]	auto[0]	auto[1]	978055	1			T3	6		T14	16964		T16	1200
auto[0]	auto[1]	auto[0]	401021	1			T3	1265		T74	19		T47	55
auto[0]	auto[1]	auto[1]	6034	1			T3	4		T74	1811		T102	12
auto[1]	auto[0]	auto[0]	12386	1			T3	99		T24	36		T32	4
auto[1]	auto[0]	auto[1]	267	1			T3	3		T24	1		T47	1
auto[1]	auto[1]	auto[0]	2624	1			T3	68		T35	4		T33	11
auto[1]	auto[1]	auto[1]	56	1			T3	4		T90	2		T92	1