Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14249

1

T6

6

T8

14

T13

6

auto[1]

10290

1

T1

20

T11

14

T32

31

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2848	1			T16	18		T35	20		T50	148
values[1]	2896	1			T15	4		T32	22		T35	40
values[2]	3218	1			T32	22		T35	22		T183	14
values[3]	3323	1			T1	20		T74	6		T38	20
values[4]	3196	1			T8	14		T35	281		T52	8
values[5]	2802	1			T6	6		T23	24		T24	53
values[6]	3207	1			T13	6		T11	14		T14	2
values[7]	3049	1			T35	20		T37	26		T105	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2483	1			T16	18		T32	22		T35	64
values[1]	3396	1			T32	22		T35	86		T115	16
values[2]	2269	1			T33	49		T34	41		T201	2
values[3]	3426	1			T24	53		T35	209		T33	55
values[4]	3713	1			T1	20		T8	14		T13	6
values[5]	3425	1			T6	6		T14	2		T39	18
values[6]	3475	1			T11	14		T12	10		T74	6
values[7]	2352	1			T15	4		T38	20		T35	105

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	105	1			T16	18		T73	17		T98	12
auto[0]	values[0]	values[1]	280	1			T139	9		T290	14		T208	12
auto[0]	values[0]	values[2]	136	1			T198	13		T292	2		T293	4
auto[0]	values[0]	values[3]	90	1			T213	16		T140	9		T253	9
auto[0]	values[0]	values[4]	420	1			T50	148		T41	20		T46	13
auto[0]	values[0]	values[5]	307	1			T33	9		T41	11		T98	12
auto[0]	values[0]	values[6]	184	1			T35	10		T164	19		T281	6
auto[0]	values[0]	values[7]	107	1			T45	14		T166	21		T26	14
auto[0]	values[1]	values[0]	189	1			T35	23		T37	10		T104	26
auto[0]	values[1]	values[1]	182	1			T32	4		T170	18		T203	8
auto[0]	values[1]	values[2]	180	1			T46	11		T294	12		T208	11
auto[0]	values[1]	values[3]	155	1			T33	11		T170	16		T180	8
auto[0]	values[1]	values[4]	297	1			T45	11		T204	8		T195	13
auto[0]	values[1]	values[5]	250	1			T34	7		T44	17		T164	13
auto[0]	values[1]	values[6]	246	1			T34	11		T190	12		T295	8
auto[0]	values[1]	values[7]	113	1			T15	4		T44	22		T185	12
auto[0]	values[2]	values[0]	254	1			T32	9		T33	12		T296	16
auto[0]	values[2]	values[1]	433	1			T35	13		T183	14		T170	17
auto[0]	values[2]	values[2]	126	1			T45	21		T46	12		T180	13
auto[0]	values[2]	values[3]	241	1			T34	12		T297	4		T45	16
auto[0]	values[2]	values[4]	183	1			T44	10		T45	22		T207	18
auto[0]	values[2]	values[5]	206	1			T46	44		T210	9		T222	6
auto[0]	values[2]	values[6]	284	1			T44	16		T164	15		T210	18
auto[0]	values[2]	values[7]	227	1			T33	8		T193	14		T215	12
auto[0]	values[3]	values[0]	281	1			T35	13		T103	14		T298	2
auto[0]	values[3]	values[1]	194	1			T102	12		T41	16		T200	4
auto[0]	values[3]	values[2]	161	1			T33	8		T34	10		T44	14
auto[0]	values[3]	values[3]	319	1			T193	9		T139	113		T182	7
auto[0]	values[3]	values[4]	308	1			T35	17		T177	4		T170	34
auto[0]	values[3]	values[5]	343	1			T33	8		T45	40		T195	6
auto[0]	values[3]	values[6]	200	1			T74	6		T41	13		T211	24
auto[0]	values[3]	values[7]	269	1			T38	20		T178	2		T191	2
auto[0]	values[4]	values[0]	148	1			T52	8		T180	14		T182	9
auto[0]	values[4]	values[1]	249	1			T35	56		T193	12		T166	14
auto[0]	values[4]	values[2]	188	1			T193	9		T213	15		T139	25
auto[0]	values[4]	values[3]	121	1			T35	6		T34	10		T41	8
auto[0]	values[4]	values[4]	194	1			T8	14		T170	16		T67	8
auto[0]	values[4]	values[5]	158	1			T101	20		T299	2		T193	21
auto[0]	values[4]	values[6]	353	1			T33	36		T34	13		T170	10
auto[0]	values[4]	values[7]	168	1			T35	12		T139	26		T300	8
auto[0]	values[5]	values[0]	91	1			T209	24		T180	10		T301	10
auto[0]	values[5]	values[1]	208	1			T115	16		T208	12		T221	12
auto[0]	values[5]	values[2]	115	1			T33	7		T201	2		T226	11
auto[0]	values[5]	values[3]	291	1			T24	53		T34	10		T184	23
auto[0]	values[5]	values[4]	223	1			T138	12		T180	12		T208	12
auto[0]	values[5]	values[5]	208	1			T6	6		T41	10		T193	12
auto[0]	values[5]	values[6]	271	1			T23	24		T41	16		T179	10
auto[0]	values[5]	values[7]	202	1			T35	37		T164	14		T291	8
auto[0]	values[6]	values[0]	255	1			T33	16		T34	12		T170	10
auto[0]	values[6]	values[1]	221	1			T195	22		T184	13		T210	9
auto[0]	values[6]	values[2]	238	1			T139	12		T180	8		T208	9
auto[0]	values[6]	values[3]	317	1			T35	18		T33	12		T46	47
auto[0]	values[6]	values[4]	170	1			T13	6		T212	8		T198	11
auto[0]	values[6]	values[5]	152	1			T14	2		T39	18		T33	5
auto[0]	values[6]	values[6]	375	1			T12	10		T33	23		T34	12
auto[0]	values[6]	values[7]	246	1			T35	9		T192	12		T184	14
auto[0]	values[7]	values[0]	221	1			T37	14		T41	13		T44	6
auto[0]	values[7]	values[1]	172	1			T105	8		T46	13		T196	5
auto[0]	values[7]	values[2]	199	1			T34	10		T195	11		T274	12
auto[0]	values[7]	values[3]	314	1			T45	9		T140	13		T287	30
auto[0]	values[7]	values[4]	293	1			T35	14		T214	6		T41	15
auto[0]	values[7]	values[5]	247	1			T172	12		T164	11		T302	12
auto[0]	values[7]	values[6]	260	1			T33	29		T41	34		T44	18
auto[0]	values[7]	values[7]	111	1			T219	10		T184	7		T187	16
auto[1]	values[0]	values[0]	83	1			T73	26		T98	8		T208	3
auto[1]	values[0]	values[1]	207	1			T139	11		T208	8		T303	4
auto[1]	values[0]	values[2]	75	1			T198	15		T26	11		T143	7
auto[1]	values[0]	values[3]	147	1			T213	7		T140	12		T253	80
auto[1]	values[0]	values[4]	320	1			T41	73		T46	7		T180	41
auto[1]	values[0]	values[5]	212	1			T33	40		T41	9		T98	10
auto[1]	values[0]	values[6]	104	1			T35	10		T164	3		T168	7
auto[1]	values[0]	values[7]	71	1			T45	6		T166	3		T26	6
auto[1]	values[1]	values[0]	87	1			T35	17		T37	12		T41	5
auto[1]	values[1]	values[1]	212	1			T32	18		T170	12		T213	8
auto[1]	values[1]	values[2]	115	1			T46	31		T208	9		T166	16
auto[1]	values[1]	values[3]	134	1			T33	24		T170	4		T180	12
auto[1]	values[1]	values[4]	196	1			T45	9		T195	7		T198	10
auto[1]	values[1]	values[5]	291	1			T34	13		T44	7		T164	7
auto[1]	values[1]	values[6]	184	1			T34	9		T184	13		T238	16
auto[1]	values[1]	values[7]	65	1			T44	8		T185	10		T226	18
auto[1]	values[2]	values[0]	138	1			T32	13		T33	13		T216	6
auto[1]	values[2]	values[1]	133	1			T35	9		T170	3		T193	7
auto[1]	values[2]	values[2]	74	1			T45	8		T46	8		T180	7
auto[1]	values[2]	values[3]	190	1			T34	8		T45	4		T193	8
auto[1]	values[2]	values[4]	183	1			T44	10		T45	32		T208	12
auto[1]	values[2]	values[5]	97	1			T46	9		T210	12		T166	6
auto[1]	values[2]	values[6]	283	1			T44	6		T164	5		T210	6
auto[1]	values[2]	values[7]	166	1			T33	12		T68	10		T193	6
auto[1]	values[3]	values[0]	154	1			T35	11		T139	13		T210	7
auto[1]	values[3]	values[1]	114	1			T41	4		T189	9		T196	9
auto[1]	values[3]	values[2]	124	1			T33	12		T34	11		T44	8
auto[1]	values[3]	values[3]	260	1			T193	12		T139	8		T182	13
auto[1]	values[3]	values[4]	157	1			T1	20		T35	20		T170	3
auto[1]	values[3]	values[5]	204	1			T33	56		T45	10		T195	18
auto[1]	values[3]	values[6]	115	1			T41	7		T213	7		T184	9
auto[1]	values[3]	values[7]	120	1			T44	12		T193	9		T196	11
auto[1]	values[4]	values[0]	91	1			T180	6		T182	11		T265	16
auto[1]	values[4]	values[1]	311	1			T35	8		T193	8		T166	6
auto[1]	values[4]	values[2]	131	1			T193	11		T213	5		T139	5
auto[1]	values[4]	values[3]	349	1			T35	180		T34	17		T41	30
auto[1]	values[4]	values[4]	272	1			T170	4		T139	7		T267	55
auto[1]	values[4]	values[5]	226	1			T193	19		T210	17		T98	6
auto[1]	values[4]	values[6]	117	1			T33	10		T34	7		T170	14
auto[1]	values[4]	values[7]	120	1			T35	19		T139	7		T304	10
auto[1]	values[5]	values[0]	69	1			T180	10		T301	15		T254	12
auto[1]	values[5]	values[1]	153	1			T40	16		T208	14		T221	8
auto[1]	values[5]	values[2]	101	1			T33	22		T226	9		T262	11
auto[1]	values[5]	values[3]	104	1			T34	13		T199	8		T184	9
auto[1]	values[5]	values[4]	139	1			T36	16		T180	8		T208	24
auto[1]	values[5]	values[5]	373	1			T41	80		T193	12		T184	6
auto[1]	values[5]	values[6]	169	1			T41	9		T193	7		T198	9
auto[1]	values[5]	values[7]	85	1			T35	8		T164	6		T226	6
auto[1]	values[6]	values[0]	172	1			T33	4		T34	8		T170	10
auto[1]	values[6]	values[1]	159	1			T195	7		T184	7		T210	13
auto[1]	values[6]	values[2]	172	1			T42	6		T139	8		T180	12
auto[1]	values[6]	values[3]	192	1			T35	5		T33	8		T46	10
auto[1]	values[6]	values[4]	114	1			T198	9		T181	12		T265	11
auto[1]	values[6]	values[5]	75	1			T33	15		T34	9		T45	10
auto[1]	values[6]	values[6]	222	1			T11	14		T33	8		T34	8
auto[1]	values[6]	values[7]	127	1			T35	20		T184	10		T210	3
auto[1]	values[7]	values[0]	145	1			T37	12		T41	27		T44	14
auto[1]	values[7]	values[1]	168	1			T46	8		T196	36		T182	6
auto[1]	values[7]	values[2]	134	1			T34	10		T43	16		T195	9
auto[1]	values[7]	values[3]	202	1			T45	47		T140	7		T187	9
auto[1]	values[7]	values[4]	244	1			T35	6		T41	17		T170	13
auto[1]	values[7]	values[5]	76	1			T164	9		T181	7		T140	19
auto[1]	values[7]	values[6]	108	1			T33	30		T41	7		T44	7
auto[1]	values[7]	values[7]	155	1			T184	20		T187	8		T143	96