Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	351	1			T38	2		T35	6		T37	1
auto[ReadAddrCrossIntoMailbox]	261	1			T38	2		T35	4		T33	4
auto[ReadAddrCrossOutOfMailbox]	258	1			T38	2		T37	1		T33	5
auto[ReadAddrCrossAllMailbox]	188	1			T38	2		T32	1		T35	5
auto[ReadAddrOutsideMailbox]	2883	1			T1	8		T6	2		T13	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2019

1

T1

4

T6

1

T13

1

auto[1]

1922

1

T1

4

T6

1

T13

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	714	1			T23	4		T38	6		T32	4
read_ops[0x0b]	639	1			T11	2		T12	2		T24	4
read_ops[0x3b]	662	1			T1	2		T6	2		T13	2
read_ops[0x6b]	671	1			T12	2		T23	2		T24	4
read_ops[0xbb]	611	1			T1	4		T24	2		T38	8
read_ops[0xeb]	644	1			T1	2		T39	2		T35	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T34	1		T179	2		T295	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T33	1		T179	2		T45	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T38	1		T193	1		T180	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T38	1		T33	1		T41	3
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T34	1		T41	2		T45	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T37	1		T33	1		T41	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	31	1			T32	1		T35	1		T193	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T34	1		T44	1		T45	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	252	1			T23	2		T38	2		T32	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	276	1			T23	2		T38	2		T32	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T35	1		T33	1		T34	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T35	2		T179	1		T46	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T35	1		T41	1		T192	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T33	1		T41	1		T192	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T34	1		T192	1		T181	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	11	1			T192	1		T193	1		T164	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T34	2		T192	1		T196	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T41	1		T192	1		T139	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	245	1			T11	1		T12	1		T24	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	211	1			T11	1		T12	1		T24	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T34	1		T45	2		T46	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T34	1		T41	2		T205	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T35	1		T33	1		T164	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T34	1		T46	1		T184	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T33	1		T41	1		T45	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T41	1		T45	1		T213	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T35	1		T45	1		T193	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T46	1		T193	1		T184	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	261	1			T1	1		T6	1		T13	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	240	1			T1	1		T6	1		T13	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T37	1		T33	1		T193	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T41	1		T193	1		T139	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T41	1		T192	1		T184	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T34	1		T192	1		T44	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T33	1		T44	1		T139	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T41	1		T193	3		T139	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T46	1		T193	1		T213	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T35	1		T193	1		T180	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	252	1			T12	1		T23	1		T24	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	247	1			T12	1		T23	1		T24	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T38	1		T35	2		T34	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T38	1		T34	1		T41	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T45	1		T193	2		T198	3
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T35	1		T193	1		T213	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T38	1		T41	1		T44	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	14	1			T38	1		T33	1		T34	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T38	1		T35	2		T192	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T38	1		T192	1		T193	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	208	1			T1	2		T24	1		T38	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	232	1			T1	2		T24	1		T38	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T41	3		T192	1		T219	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T35	1		T192	1		T219	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T34	1		T41	1		T193	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T35	1		T33	1		T45	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T41	1		T198	1		T210	3
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T33	1		T45	1		T46	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T44	1		T193	1		T198	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T34	1		T45	1		T193	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	250	1			T1	1		T39	1		T73	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	209	1			T1	1		T39	1		T35	4