Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2858161	1			T1	1		T2	1		T3	12685
all_pins[1]	2858161	1			T1	1		T2	1		T3	12685
all_pins[2]	2858161	1			T1	1		T2	1		T3	12685
all_pins[3]	2858161	1			T1	1		T2	1		T3	12685
all_pins[4]	2858161	1			T1	1		T2	1		T3	12685
all_pins[5]	2858161	1			T1	1		T2	1		T3	12685
all_pins[6]	2858161	1			T1	1		T2	1		T3	12685
all_pins[7]	2858161	1			T1	1		T2	1		T3	12685

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22635837	1			T1	8		T2	8		T3	101480
values[0x1]	229451	1			T18	16		T77	26		T78	30
transitions[0x0=>0x1]	228025	1			T18	12		T77	20		T78	21
transitions[0x1=>0x0]	228033	1			T18	12		T77	20		T78	21

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2857209	1			T1	1		T2	1		T3	12685
all_pins[0]	values[0x1]	952	1			T77	7		T78	6		T33	1
all_pins[0]	transitions[0x0=>0x1]	747	1			T77	6		T78	2		T33	1
all_pins[0]	transitions[0x1=>0x0]	215	1			T77	1		T78	2		T170	3
all_pins[1]	values[0x0]	2857741	1			T1	1		T2	1		T3	12685
all_pins[1]	values[0x1]	420	1			T77	2		T78	6		T170	4
all_pins[1]	transitions[0x0=>0x1]	306	1			T77	2		T78	5		T170	4
all_pins[1]	transitions[0x1=>0x0]	175	1			T77	5		T78	1		T33	3
all_pins[2]	values[0x0]	2857872	1			T1	1		T2	1		T3	12685
all_pins[2]	values[0x1]	289	1			T77	5		T78	2		T33	3
all_pins[2]	transitions[0x0=>0x1]	244	1			T77	4		T78	2		T33	3
all_pins[2]	transitions[0x1=>0x0]	158	1			T18	5		T77	1		T78	2
all_pins[3]	values[0x0]	2857958	1			T1	1		T2	1		T3	12685
all_pins[3]	values[0x1]	203	1			T18	5		T77	2		T78	2
all_pins[3]	transitions[0x0=>0x1]	134	1			T18	2		T77	2		T78	1
all_pins[3]	transitions[0x1=>0x0]	162	1			T18	2		T77	4		T78	3
all_pins[4]	values[0x0]	2857930	1			T1	1		T2	1		T3	12685
all_pins[4]	values[0x1]	231	1			T18	5		T77	4		T78	4
all_pins[4]	transitions[0x0=>0x1]	187	1			T18	5		T77	2		T78	2
all_pins[4]	transitions[0x1=>0x0]	1878	1			T18	1		T78	2		T170	3
all_pins[5]	values[0x0]	2856239	1			T1	1		T2	1		T3	12685
all_pins[5]	values[0x1]	1922	1			T18	1		T77	2		T78	4
all_pins[5]	transitions[0x0=>0x1]	1076	1			T77	1		T78	3		T170	3
all_pins[5]	transitions[0x1=>0x0]	224382	1			T78	4		T33	2		T170	3
all_pins[6]	values[0x0]	2632933	1			T1	1		T2	1		T3	12685
all_pins[6]	values[0x1]	225228	1			T18	1		T77	1		T78	5
all_pins[6]	transitions[0x0=>0x1]	225188	1			T18	1		T77	1		T78	5
all_pins[6]	transitions[0x1=>0x0]	166	1			T18	4		T77	3		T78	1
all_pins[7]	values[0x0]	2857955	1			T1	1		T2	1		T3	12685
all_pins[7]	values[0x1]	206	1			T18	4		T77	3		T78	1
all_pins[7]	transitions[0x0=>0x1]	143	1			T18	4		T77	2		T78	1
all_pins[7]	transitions[0x1=>0x0]	897	1			T77	6		T78	6		T33	1