Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3196	1			T14	2		T15	4		T16	18
values[1]	2709	1			T6	6		T24	53		T39	18
values[2]	2770	1			T35	86		T50	148		T177	4
values[3]	3334	1			T8	14		T12	10		T35	68
values[4]	2969	1			T74	6		T23	24		T32	22
values[5]	3035	1			T11	14		T105	8		T33	49
values[6]	3105	1			T13	6		T35	20		T37	26
values[7]	3421	1			T1	20		T35	88		T115	16

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3373	1			T16	18		T23	24		T32	22
values[1]	3088	1			T38	20		T35	40		T73	20
values[2]	3260	1			T74	6		T24	53		T32	22
values[3]	2995	1			T6	6		T13	6		T14	2
values[4]	3860	1			T11	14		T12	10		T35	24
values[5]	2486	1			T1	20		T39	18		T52	8
values[6]	3163	1			T178	2		T37	48		T33	64
values[7]	2314	1			T8	14		T15	4		T103	14

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24132

1

T1

20

T6

6

T8

14

auto[1]

407

1

T32

1

T35

8

T37

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[7]]	[values[7]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	331	1			T16	18		T32	22		T179	10
auto[0]	values[0]	values[1]	511	1			T38	20		T180	20		T181	48
auto[0]	values[0]	values[2]	534	1			T164	21		T139	20		T182	21
auto[0]	values[0]	values[3]	346	1			T14	2		T35	20		T183	14
auto[0]	values[0]	values[4]	467	1			T41	26		T184	20		T185	20
auto[0]	values[0]	values[5]	388	1			T102	12		T172	12		T139	20
auto[0]	values[0]	values[6]	343	1			T34	20		T44	25		T180	20
auto[0]	values[0]	values[7]	225	1			T15	4		T34	20		T45	19
auto[0]	values[1]	values[0]	423	1			T186	91		T187	42		T188	70
auto[0]	values[1]	values[1]	466	1			T45	35		T189	20		T139	30
auto[0]	values[1]	values[2]	233	1			T24	53		T35	29		T41	66
auto[0]	values[1]	values[3]	291	1			T6	6		T170	24		T44	17
auto[0]	values[1]	values[4]	190	1			T35	23		T166	20		T168	20
auto[0]	values[1]	values[5]	258	1			T39	18		T190	12		T45	22
auto[0]	values[1]	values[6]	358	1			T178	2		T41	20		T191	2
auto[0]	values[1]	values[7]	443	1			T192	12		T193	23		T194	14
auto[0]	values[2]	values[0]	405	1			T50	148		T44	27		T184	31
auto[0]	values[2]	values[1]	229	1			T180	72		T166	22		T181	20
auto[0]	values[2]	values[2]	519	1			T35	22		T33	40		T170	20
auto[0]	values[2]	values[3]	433	1			T35	64		T73	22		T34	18
auto[0]	values[2]	values[4]	311	1			T170	20		T195	20		T196	41
auto[0]	values[2]	values[5]	303	1			T181	20		T168	29		T197	28
auto[0]	values[2]	values[6]	328	1			T37	22		T34	18		T44	20
auto[0]	values[2]	values[7]	194	1			T177	4		T41	21		T198	19
auto[0]	values[3]	values[0]	686	1			T35	45		T101	20		T33	29
auto[0]	values[3]	values[1]	274	1			T73	20		T33	35		T46	42
auto[0]	values[3]	values[2]	310	1			T104	26		T33	66		T34	20
auto[0]	values[3]	values[3]	439	1			T35	23		T34	21		T193	24
auto[0]	values[3]	values[4]	544	1			T12	10		T33	23		T40	12
auto[0]	values[3]	values[5]	390	1			T52	8		T33	20		T184	24
auto[0]	values[3]	values[6]	250	1			T199	8		T200	4		T98	22
auto[0]	values[3]	values[7]	385	1			T8	14		T201	2		T45	20
auto[0]	values[4]	values[0]	512	1			T23	24		T35	183		T198	20
auto[0]	values[4]	values[1]	349	1			T33	31		T170	21		T202	14
auto[0]	values[4]	values[2]	434	1			T74	6		T32	21		T34	20
auto[0]	values[4]	values[3]	267	1			T35	20		T44	21		T193	20
auto[0]	values[4]	values[4]	555	1			T41	61		T170	57		T193	20
auto[0]	values[4]	values[5]	203	1			T41	23		T189	19		T180	23
auto[0]	values[4]	values[6]	386	1			T45	34		T198	20		T196	20
auto[0]	values[4]	values[7]	220	1			T203	8		T193	20		T164	20
auto[0]	values[5]	values[0]	313	1			T41	19		T204	8		T184	21
auto[0]	values[5]	values[1]	378	1			T44	24		T205	12		T206	10
auto[0]	values[5]	values[2]	520	1			T193	20		T207	18		T208	35
auto[0]	values[5]	values[3]	339	1			T209	24		T164	20		T210	20
auto[0]	values[5]	values[4]	424	1			T11	14		T211	24		T43	14
auto[0]	values[5]	values[5]	315	1			T105	8		T68	10		T139	39
auto[0]	values[5]	values[6]	315	1			T46	53		T193	17		T212	8
auto[0]	values[5]	values[7]	382	1			T33	48		T46	57		T188	20
auto[0]	values[6]	values[0]	340	1			T45	20		T195	29		T213	23
auto[0]	values[6]	values[1]	356	1			T35	19		T213	25		T184	22
auto[0]	values[6]	values[2]	337	1			T214	6		T180	52		T215	20
auto[0]	values[6]	values[3]	245	1			T13	6		T34	23		T164	20
auto[0]	values[6]	values[4]	601	1			T34	20		T216	6		T44	22
auto[0]	values[6]	values[5]	235	1			T138	12		T217	6		T184	21
auto[0]	values[6]	values[6]	691	1			T37	23		T33	64		T170	49
auto[0]	values[6]	values[7]	252	1			T36	16		T33	25		T170	20
auto[0]	values[7]	values[0]	301	1			T35	29		T115	16		T170	28
auto[0]	values[7]	values[1]	461	1			T35	20		T34	27		T41	27
auto[0]	values[7]	values[2]	334	1			T45	20		T166	24		T218	20
auto[0]	values[7]	values[3]	582	1			T35	36		T34	20		T219	10
auto[0]	values[7]	values[4]	700	1			T33	20		T220	22		T221	104
auto[0]	values[7]	values[5]	350	1			T1	20		T33	32		T41	38
auto[0]	values[7]	values[6]	445	1			T41	129		T44	25		T195	20
auto[0]	values[7]	values[7]	183	1			T103	14		T222	6		T166	21
auto[1]	values[0]	values[0]	12	1			T45	1		T223	8		T139	1
auto[1]	values[0]	values[1]	7	1			T224	1		T143	2		T225	2
auto[1]	values[0]	values[2]	6	1			T164	1		T182	1		T226	1
auto[1]	values[0]	values[3]	5	1			T45	2		T227	2		T228	1
auto[1]	values[0]	values[4]	7	1			T41	1		T229	3		T230	2
auto[1]	values[0]	values[5]	3	1			T231	1		T232	2		-	-
auto[1]	values[0]	values[6]	6	1			T166	2		T233	1		T234	3
auto[1]	values[0]	values[7]	5	1			T45	1		T187	1		T233	1
auto[1]	values[1]	values[0]	5	1			T188	1		T235	2		T236	2
auto[1]	values[1]	values[1]	15	1			T45	1		T237	2		T185	1
auto[1]	values[1]	values[2]	2	1			T180	2		-	-		-	-
auto[1]	values[1]	values[3]	8	1			T44	3		T210	2		T238	2
auto[1]	values[1]	values[4]	2	1			T35	1		T239	1		-	-
auto[1]	values[1]	values[5]	5	1			T240	2		T236	3		-	-
auto[1]	values[1]	values[6]	3	1			T140	1		T241	2		-	-
auto[1]	values[1]	values[7]	7	1			T193	2		T194	2		T227	1
auto[1]	values[2]	values[0]	7	1			T44	3		T184	1		T143	3
auto[1]	values[2]	values[1]	2	1			T180	2		-	-		-	-
auto[1]	values[2]	values[2]	12	1			T193	2		T169	4		T224	3
auto[1]	values[2]	values[3]	8	1			T73	1		T34	2		T242	1
auto[1]	values[2]	values[4]	5	1			T221	2		T181	2		T243	1
auto[1]	values[2]	values[5]	3	1			T168	2		T232	1		-	-
auto[1]	values[2]	values[6]	7	1			T34	2		T228	3		T235	2
auto[1]	values[2]	values[7]	4	1			T198	1		T244	1		T245	2
auto[1]	values[3]	values[0]	16	1			T195	2		T184	1		T185	2
auto[1]	values[3]	values[1]	4	1			T243	1		T246	2		T247	1
auto[1]	values[3]	values[2]	2	1			T248	1		T249	1		-	-
auto[1]	values[3]	values[3]	5	1			T221	1		T188	1		T243	1
auto[1]	values[3]	values[4]	14	1			T33	3		T40	4		T182	3
auto[1]	values[3]	values[5]	4	1			T243	2		T250	2		-	-
auto[1]	values[3]	values[6]	7	1			T168	2		T251	5		-	-
auto[1]	values[3]	values[7]	4	1			T46	2		T252	2		-	-
auto[1]	values[4]	values[0]	8	1			T35	3		T26	3		T239	1
auto[1]	values[4]	values[1]	9	1			T182	2		T226	3		T26	1
auto[1]	values[4]	values[2]	7	1			T32	1		T182	2		T253	2
auto[1]	values[4]	values[3]	2	1			T44	1		T143	1		-	-
auto[1]	values[4]	values[4]	4	1			T182	1		T254	2		T255	1
auto[1]	values[4]	values[5]	7	1			T41	2		T189	1		T256	2
auto[1]	values[4]	values[6]	1	1			T257	1		-	-		-	-
auto[1]	values[4]	values[7]	5	1			T208	3		T243	1		T232	1
auto[1]	values[5]	values[0]	5	1			T41	1		T184	1		T258	1
auto[1]	values[5]	values[1]	8	1			T99	3		T235	1		T259	2
auto[1]	values[5]	values[2]	4	1			T208	1		T26	1		T143	2
auto[1]	values[5]	values[3]	8	1			T182	1		T238	4		T260	2
auto[1]	values[5]	values[4]	10	1			T43	2		T210	1		T261	2
auto[1]	values[5]	values[5]	5	1			T139	1		T244	1		T228	3
auto[1]	values[5]	values[6]	6	1			T193	3		T213	1		T140	1
auto[1]	values[5]	values[7]	3	1			T33	1		T262	1		T263	1
auto[1]	values[6]	values[0]	4	1			T188	1		T169	1		T228	2
auto[1]	values[6]	values[1]	10	1			T35	1		T264	4		T262	3
auto[1]	values[6]	values[2]	4	1			T265	2		T235	1		T248	1
auto[1]	values[6]	values[3]	3	1			T253	2		T266	1		-	-
auto[1]	values[6]	values[4]	11	1			T267	1		T258	2		T231	4
auto[1]	values[6]	values[5]	3	1			T184	1		T239	2		-	-
auto[1]	values[6]	values[6]	11	1			T37	3		T170	3		T196	1
auto[1]	values[6]	values[7]	2	1			T63	2		-	-		-	-
auto[1]	values[7]	values[0]	5	1			T35	2		T170	2		T168	1
auto[1]	values[7]	values[1]	9	1			T41	1		T262	4		T268	2
auto[1]	values[7]	values[2]	2	1			T188	1		T228	1		-	-
auto[1]	values[7]	values[3]	14	1			T35	1		T210	1		T215	1
auto[1]	values[7]	values[4]	15	1			T187	3		T99	2		T229	1
auto[1]	values[7]	values[5]	14	1			T33	1		T42	2		T45	1
auto[1]	values[7]	values[6]	6	1			T41	1		T44	1		T210	1