Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1908

1

T2

1

T3

7

T7

8

auto[1]

1897

1

T2

2

T3

9

T7

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2058

1

T3

14

T7

12

T17

12

auto[1]

1747

1

T2

3

T3

2

T7

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3026

1

T2

3

T3

10

T7

10

auto[1]

779

1

T3

6

T7

3

T17

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	750	1			T2	1		T7	3		T10	8
valid[1]	777	1			T3	2		T7	2		T10	7
valid[2]	763	1			T2	1		T3	4		T7	2
valid[3]	728	1			T2	1		T3	3		T7	2
valid[4]	787	1			T3	7		T7	4		T10	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	113	1			T7	1		T17	2		T32	1
auto[0]	auto[0]	valid[0]	auto[1]	177	1			T2	1		T10	5		T20	4
auto[0]	auto[0]	valid[1]	auto[0]	126	1			T7	1		T17	2		T32	2
auto[0]	auto[0]	valid[1]	auto[1]	187	1			T10	2		T20	2		T22	4
auto[0]	auto[0]	valid[2]	auto[0]	126	1			T3	2		T7	1		T17	1
auto[0]	auto[0]	valid[2]	auto[1]	176	1			T7	1		T10	4		T20	4
auto[0]	auto[0]	valid[3]	auto[0]	125	1			T7	1		T17	1		T32	1
auto[0]	auto[0]	valid[3]	auto[1]	154	1			T10	3		T20	1		T22	5
auto[0]	auto[0]	valid[4]	auto[0]	139	1			T3	1		T7	2		T17	1
auto[0]	auto[0]	valid[4]	auto[1]	183	1			T3	1		T10	2		T20	2
auto[0]	auto[1]	valid[0]	auto[0]	132	1			T17	1		T32	3		T97	3
auto[0]	auto[1]	valid[0]	auto[1]	156	1			T10	3		T85	1		T87	1
auto[0]	auto[1]	valid[1]	auto[0]	125	1			T3	1		T49	1		T97	1
auto[0]	auto[1]	valid[1]	auto[1]	187	1			T10	5		T20	6		T22	2
auto[0]	auto[1]	valid[2]	auto[0]	133	1			T3	1		T32	2		T49	1
auto[0]	auto[1]	valid[2]	auto[1]	172	1			T2	1		T10	2		T20	3
auto[0]	auto[1]	valid[3]	auto[0]	127	1			T3	1		T7	1		T32	2
auto[0]	auto[1]	valid[3]	auto[1]	172	1			T2	1		T10	2		T20	2
auto[0]	auto[1]	valid[4]	auto[0]	133	1			T3	2		T7	2		T32	1
auto[0]	auto[1]	valid[4]	auto[1]	183	1			T3	1		T10	3		T20	3
auto[1]	auto[0]	valid[0]	auto[0]	96	1			T17	1		T32	1		T37	1
auto[1]	auto[0]	valid[1]	auto[0]	82	1			T7	1		T32	1		T49	1
auto[1]	auto[0]	valid[2]	auto[0]	72	1			T3	1		T97	2		T37	1
auto[1]	auto[0]	valid[3]	auto[0]	82	1			T3	2		T32	1		T97	1
auto[1]	auto[0]	valid[4]	auto[0]	70	1			T17	1		T32	1		T35	1
auto[1]	auto[1]	valid[0]	auto[0]	76	1			T7	2		T32	2		T49	1
auto[1]	auto[1]	valid[1]	auto[0]	70	1			T3	1		T17	1		T32	2
auto[1]	auto[1]	valid[2]	auto[0]	84	1			T17	1		T32	1		T37	3
auto[1]	auto[1]	valid[3]	auto[0]	68	1			T49	1		T37	1		T33	1
auto[1]	auto[1]	valid[4]	auto[0]	79	1			T3	2		T32	1		T37	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal