Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50388

1

T3

148

T7

268

T17

236

auto[1]

18797

1

T2

43

T3

24

T7

44

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50616

1

T2

43

T3

118

T7

209

auto[1]

18569

1

T3

54

T7

103

T17

84

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35388	1			T2	29		T3	86		T7	153
others[1]	5861	1			T2	4		T3	11		T7	34
others[2]	5885	1			T2	2		T3	14		T7	18
others[3]	6642	1			T2	2		T3	16		T7	39
interest[1]	3841	1			T2	2		T3	7		T7	18
interest[4]	23196	1			T2	20		T3	65		T7	103
interest[64]	11568	1			T2	4		T3	38		T7	50

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16128	1			T3	48		T7	79		T17	75
auto[0]	auto[0]	others[1]	2693	1			T3	4		T7	15		T17	13
auto[0]	auto[0]	others[2]	2748	1			T3	9		T7	11		T17	14
auto[0]	auto[0]	others[3]	3093	1			T3	9		T7	24		T17	14
auto[0]	auto[0]	interest[1]	1836	1			T3	3		T7	9		T17	10
auto[0]	auto[0]	interest[4]	10498	1			T3	36		T7	54		T17	42
auto[0]	auto[0]	interest[64]	5321	1			T3	21		T7	27		T17	26
auto[0]	auto[1]	others[0]	9796	1			T2	29		T3	14		T7	23
auto[0]	auto[1]	others[1]	1580	1			T2	4		T3	1		T7	6
auto[0]	auto[1]	others[2]	1561	1			T2	2		T3	1		T7	1
auto[0]	auto[1]	others[3]	1763	1			T2	2		T3	2		T7	5
auto[0]	auto[1]	interest[1]	1003	1			T2	2		T3	3		T7	2
auto[0]	auto[1]	interest[4]	6448	1			T2	20		T3	11		T7	11
auto[0]	auto[1]	interest[64]	3094	1			T2	4		T3	3		T7	7
auto[1]	auto[0]	others[0]	9464	1			T3	24		T7	51		T17	41
auto[1]	auto[0]	others[1]	1588	1			T3	6		T7	13		T17	10
auto[1]	auto[0]	others[2]	1576	1			T3	4		T7	6		T17	7
auto[1]	auto[0]	others[3]	1786	1			T3	5		T7	10		T17	8
auto[1]	auto[0]	interest[1]	1002	1			T3	1		T7	7		T17	2
auto[1]	auto[0]	interest[4]	6250	1			T3	18		T7	38		T17	30
auto[1]	auto[0]	interest[64]	3153	1			T3	14		T7	16		T17	16

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal