Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	856	1			T18	10		T77	14		T78	17
all_values[1]	856	1			T18	10		T77	14		T78	17
all_values[2]	856	1			T18	10		T77	14		T78	17
all_values[3]	856	1			T18	10		T77	14		T78	17
all_values[4]	856	1			T18	10		T77	14		T78	17
all_values[5]	856	1			T18	10		T77	14		T78	17
all_values[6]	856	1			T18	10		T77	14		T78	17
all_values[7]	856	1			T18	10		T77	14		T78	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3557

1

T18

34

T77

56

T78

65

auto[1]

3291

1

T18

46

T77

56

T78

71

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2760

1

T18

44

T77

41

T78

65

auto[1]

4088

1

T18

36

T77

71

T78

71

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3929

1

T18

54

T77

61

T78

83

auto[1]

2919

1

T18

26

T77

51

T78

53

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	156	1			T77	2		T78	2		T33	3
all_values[0]	auto[0]	auto[0]	auto[1]	79	1			T18	1		T78	2		T92	2
all_values[0]	auto[0]	auto[1]	auto[0]	158	1			T18	4		T77	1		T78	2
all_values[0]	auto[0]	auto[1]	auto[1]	97	1			T77	4		T78	3		T170	2
all_values[0]	auto[1]	auto[0]	auto[1]	170	1			T18	3		T77	2		T78	5
all_values[0]	auto[1]	auto[1]	auto[1]	196	1			T18	2		T77	5		T78	3
all_values[1]	auto[0]	auto[0]	auto[0]	166	1			T18	3		T77	2		T78	6
all_values[1]	auto[0]	auto[0]	auto[1]	80	1			T77	1		T78	1		T170	3
all_values[1]	auto[0]	auto[1]	auto[0]	163	1			T18	5		T77	3		T78	2
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T77	1		T78	2		T170	1
all_values[1]	auto[1]	auto[0]	auto[1]	186	1			T77	5		T78	2		T33	2
all_values[1]	auto[1]	auto[1]	auto[1]	176	1			T18	2		T77	2		T78	4
all_values[2]	auto[0]	auto[0]	auto[0]	183	1			T18	2		T77	1		T78	6
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T77	3		T170	4		T92	4
all_values[2]	auto[0]	auto[1]	auto[0]	158	1			T18	6		T78	7		T33	1
all_values[2]	auto[0]	auto[1]	auto[1]	59	1			T77	3		T78	1		T33	3
all_values[2]	auto[1]	auto[0]	auto[1]	211	1			T18	1		T77	4		T78	1
all_values[2]	auto[1]	auto[1]	auto[1]	168	1			T18	1		T77	3		T78	2
all_values[3]	auto[0]	auto[0]	auto[0]	154	1			T77	5		T78	5		T170	2
all_values[3]	auto[0]	auto[0]	auto[1]	87	1			T18	2		T77	1		T78	1
all_values[3]	auto[0]	auto[1]	auto[0]	138	1			T18	2		T77	2		T78	6
all_values[3]	auto[0]	auto[1]	auto[1]	91	1			T18	1		T77	1		T78	1
all_values[3]	auto[1]	auto[0]	auto[1]	212	1			T18	1		T77	4		T78	2
all_values[3]	auto[1]	auto[1]	auto[1]	174	1			T18	4		T77	1		T78	2
all_values[4]	auto[0]	auto[0]	auto[0]	182	1			T18	1		T77	1		T78	2
all_values[4]	auto[0]	auto[0]	auto[1]	85	1			T18	1		T77	2		T78	1
all_values[4]	auto[0]	auto[1]	auto[0]	138	1			T18	3		T77	2		T78	3
all_values[4]	auto[0]	auto[1]	auto[1]	94	1			T18	1		T78	2		T170	1
all_values[4]	auto[1]	auto[0]	auto[1]	177	1			T18	1		T77	3		T78	4
all_values[4]	auto[1]	auto[1]	auto[1]	180	1			T18	3		T77	6		T78	5
all_values[5]	auto[0]	auto[0]	auto[0]	249	1			T18	6		T77	4		T78	4
all_values[5]	auto[0]	auto[1]	auto[0]	226	1			T18	2		T77	4		T78	5
all_values[5]	auto[1]	auto[0]	auto[1]	196	1			T18	1		T77	4		T78	4
all_values[5]	auto[1]	auto[1]	auto[1]	185	1			T18	1		T77	2		T78	4
all_values[6]	auto[0]	auto[0]	auto[0]	184	1			T18	5		T77	1		T78	4
all_values[6]	auto[0]	auto[0]	auto[1]	86	1			T18	1		T77	2		T170	2
all_values[6]	auto[0]	auto[1]	auto[0]	173	1			T18	2		T77	6		T78	4
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T78	2		T33	2		T170	1
all_values[6]	auto[1]	auto[0]	auto[1]	189	1			T77	2		T78	3		T33	1
all_values[6]	auto[1]	auto[1]	auto[1]	149	1			T18	2		T77	3		T78	4
all_values[7]	auto[0]	auto[0]	auto[0]	175	1			T18	2		T77	4		T78	3
all_values[7]	auto[0]	auto[0]	auto[1]	91	1			T18	1		T77	1		T78	1
all_values[7]	auto[0]	auto[1]	auto[0]	157	1			T18	1		T77	3		T78	4
all_values[7]	auto[0]	auto[1]	auto[1]	83	1			T18	2		T77	1		T78	1
all_values[7]	auto[1]	auto[0]	auto[1]	182	1			T18	2		T77	2		T78	6
all_values[7]	auto[1]	auto[1]	auto[1]	168	1			T18	2		T77	3		T78	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal