Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2411840	1			T1	2		T2	1		T3	1
all_values[1]	2411840	1			T1	2		T2	1		T3	1
all_values[2]	2411840	1			T1	2		T2	1		T3	1
all_values[3]	2411840	1			T1	2		T2	1		T3	1
all_values[4]	2411840	1			T1	2		T2	1		T3	1
all_values[5]	2411840	1			T1	2		T2	1		T3	1
all_values[6]	2411840	1			T1	2		T2	1		T3	1
all_values[7]	2411840	1			T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19048383

1

T1

16

T2

8

T3

8

auto[1]

246337

1

T11

75

T27

80403

T34

23

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19273810

1

T1

16

T2

8

T3

8

auto[1]

20910

1

T4

75

T11

240

T16

109

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2369240	1			T1	2		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	10782	1			T4	25		T11	110		T16	109
all_values[0]	auto[1]	auto[0]	31484	1			T11	4		T27	13332		T34	1
all_values[0]	auto[1]	auto[1]	334	1			T11	7		T27	67		T55	1
all_values[1]	auto[0]	auto[0]	2400004	1			T1	2		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	5247	1			T4	25		T11	55		T19	66
all_values[1]	auto[1]	auto[0]	6398	1			T11	3		T27	3		T34	3
all_values[1]	auto[1]	auto[1]	191	1			T11	4		T27	3		T34	1
all_values[2]	auto[0]	auto[0]	2365563	1			T1	2		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2058	1			T4	25		T11	6		T19	19
all_values[2]	auto[1]	auto[0]	43962	1			T11	4		T27	13393		T55	5
all_values[2]	auto[1]	auto[1]	257	1			T11	7		T27	4		T36	2
all_values[3]	auto[0]	auto[0]	2370517	1			T1	2		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	192	1			T11	4		T27	2		T154	2
all_values[3]	auto[1]	auto[0]	40947	1			T11	8		T27	13398		T34	3
all_values[3]	auto[1]	auto[1]	184	1			T11	2		T55	2		T36	2
all_values[4]	auto[0]	auto[0]	2371414	1			T1	2		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	230	1			T11	9		T27	4		T34	2
all_values[4]	auto[1]	auto[0]	40002	1			T11	4		T27	13397		T55	4
all_values[4]	auto[1]	auto[1]	194	1			T11	4		T36	1		T154	4
all_values[5]	auto[0]	auto[0]	2385794	1			T1	2		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	287	1			T11	5		T18	1		T20	1
all_values[5]	auto[1]	auto[0]	25575	1			T11	4		T27	13399		T34	3
all_values[5]	auto[1]	auto[1]	184	1			T11	4		T27	2		T34	2
all_values[6]	auto[0]	auto[0]	2397176	1			T1	2		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	203	1			T11	2		T36	1		T154	2
all_values[6]	auto[1]	auto[0]	14281	1			T11	4		T27	5		T34	3
all_values[6]	auto[1]	auto[1]	180	1			T11	9		T27	1		T34	2
all_values[7]	auto[0]	auto[0]	2369484	1			T1	2		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	192	1			T11	11		T27	5		T36	3
all_values[7]	auto[1]	auto[0]	41969	1			T11	6		T27	13398		T34	3
all_values[7]	auto[1]	auto[1]	195	1			T11	1		T27	1		T34	2