Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	29766	1			T2	8		T4	15		T8	4
auto[SpiFlashAddrCfg]	6173	1			T2	8		T4	12		T11	80
auto[SpiFlashAddr3b]	7660	1			T1	1		T4	4		T11	83
auto[SpiFlashAddr4b]	6296	1			T1	1		T2	6		T4	12

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28018

1

T1

2

T4

14

T8

4

auto[1]

21877

1

T2

22

T4

29

T11

285

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26509

1

T1

1

T2

10

T4

21

auto[1]

23386

1

T1

1

T2

12

T4

22

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	33534	1			T2	6		T4	20		T8	4
values[1]	871	1			T11	11		T15	4		T16	1
values[2]	1235	1			T4	1		T11	13		T15	4
values[3]	1162	1			T4	6		T11	17		T15	1
values[4]	1219	1			T1	1		T2	6		T11	15
values[5]	1228	1			T11	6		T15	7		T16	1
values[6]	1179	1			T4	2		T11	15		T15	2
values[7]	1182	1			T4	1		T11	15		T15	5
values[8]	8285	1			T1	1		T2	10		T4	13

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27196

1

T2

22

T4

43

T8

4

auto[1]

22699

1

T1

2

T11

431

T15

274

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

48172

1

T1

2

T2

22

T4

42

write

1723

1

T4

1

T11

11

T15

14

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16337

1

T1

2

T2

14

T4

23

valids[0x1]

33558

1

T2

8

T4

20

T8

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1365	1			T2	2		T8	2		T11	14
internal_process_ops[0x5a]	1328	1			T11	14		T15	6		T39	1
internal_process_ops[0x05]	18272	1			T2	2		T4	4		T10	2
internal_process_ops[0x35]	1327	1			T4	1		T11	11		T15	5
internal_process_ops[0x15]	1242	1			T2	2		T8	2		T10	4
internal_process_ops[0x03]	905	1			T4	2		T11	6		T15	3
internal_process_ops[0x0b]	918	1			T4	3		T11	11		T15	2
internal_process_ops[0x3b]	887	1			T1	1		T2	4		T4	1
internal_process_ops[0x6b]	904	1			T4	6		T11	7		T15	6
internal_process_ops[0xbb]	893	1			T1	1		T4	2		T11	14
internal_process_ops[0xeb]	905	1			T2	2		T11	3		T39	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49055

1

T1

2

T2

22

T4

42

auto[1]

840

1

T4

1

T11

4

T15

5

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48233

1

T1

2

T2

22

T4

42

auto[1]

1662

1

T4

1

T11

16

T15

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10014

1

T4

6

T8

4

T10

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5540

1

T2

8

T4

8

T11

14

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1755

1

T4

2

T11

6

T159

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1486

1

T2

8

T4

10

T11

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2153

1

T11

2

T31

4

T104

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1918

1

T4

4

T11

12

T29

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1839

1

T4

5

T11

13

T159

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1639

1

T2

6

T4

7

T11

10

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

54

1

T27

1

T28

2

T34

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

47

1

T4

1

T27

2

T35

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

45

1

T28

1

T35

1

T36

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

58

1

T11

1

T29

2

T27

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

56

1

T41

2

T54

2

T195

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

54

1

T11

2

T27

2

T28

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

49

1

T11

2

T27

1

T165

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

52

1

T35

1

T37

1

T71

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

55

1

T27

4

T28

1

T41

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

55

1

T35

3

T36

1

T165

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

51

1

T11

2

T27

2

T28

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

54

1

T27

3

T38

4

T71

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

56

1

T11

1

T183

2

T71

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

56

1

T27

1

T28

4

T35

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

65

1

T27

3

T28

3

T165

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

45

1

T30

2

T34

1

T37

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7232

1

T11

102

T15

201

T39

19

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6555

1

T11

149

T15

10

T39

6

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1248

1

T11

33

T15

8

T39

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1273

1

T11

30

T15

5

T39

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1633

1

T1

1

T11

40

T15

10

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1494

1

T11

25

T15

9

T39

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1255

1

T1

1

T11

18

T15

8

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1138

1

T11

31

T15

9

T39

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

65

1

T15

2

T36

1

T244

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

57

1

T34

1

T89

2

T36

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

51

1

T15

2

T39

1

T36

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

48

1

T89

1

T36

2

T244

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

50

1

T131

1

T245

3

T246

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

47

1

T44

2

T34

2

T36

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

58

1

T15

1

T19

2

T36

7

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

45

1

T11

1

T19

1

T44

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

63

1

T15

1

T39

2

T36

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

73

1

T15

2

T39

1

T19

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

55

1

T11

2

T15

3

T19

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

56

1

T15

1

T19

3

T34

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

43

1

T36

6

T129

1

T131

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

58

1

T15

2

T244

2

T247

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

67

1

T44

1

T37

1

T129

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

35

1

T19

1

T244

1

T128

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3444	1			T4	7		T11	16		T14	4
auto[0]	values[0]	valids[0x1]	14431	1			T2	6		T4	13		T8	4
auto[0]	values[1]	valids[0x1]	425	1			T11	1		T27	14		T28	4
auto[0]	values[2]	valids[0x0]	431	1			T29	2		T27	5		T28	7
auto[0]	values[2]	valids[0x1]	244	1			T4	1		T27	4		T28	4
auto[0]	values[3]	valids[0x0]	492	1			T4	6		T159	4		T30	4
auto[0]	values[3]	valids[0x1]	221	1			T11	1		T27	10		T28	2
auto[0]	values[4]	valids[0x0]	429	1			T2	6		T11	3		T27	15
auto[0]	values[4]	valids[0x1]	282	1			T11	2		T27	4		T28	10
auto[0]	values[5]	valids[0x0]	427	1			T27	8		T28	12		T34	5
auto[0]	values[5]	valids[0x1]	249	1			T27	8		T28	5		T34	2
auto[0]	values[6]	valids[0x0]	456	1			T4	2		T11	2		T104	4
auto[0]	values[6]	valids[0x1]	246	1			T27	4		T28	1		T34	2
auto[0]	values[7]	valids[0x0]	455	1			T4	1		T11	2		T27	6
auto[0]	values[7]	valids[0x1]	243	1			T11	1		T31	4		T27	7
auto[0]	values[8]	valids[0x0]	2982	1			T2	8		T4	7		T11	11
auto[0]	values[8]	valids[0x1]	1739	1			T2	2		T4	6		T11	11
auto[1]	values[0]	valids[0x0]	3381	1			T11	73		T15	23		T39	12
auto[1]	values[0]	valids[0x1]	12278	1			T11	209		T15	212		T39	19
auto[1]	values[1]	valids[0x1]	446	1			T11	10		T15	4		T16	1
auto[1]	values[2]	valids[0x0]	314	1			T11	6		T15	1		T39	3
auto[1]	values[2]	valids[0x1]	246	1			T11	7		T15	3		T39	2
auto[1]	values[3]	valids[0x0]	265	1			T11	12		T16	4		T19	5
auto[1]	values[3]	valids[0x1]	184	1			T11	4		T15	1		T44	5
auto[1]	values[4]	valids[0x0]	295	1			T1	1		T11	5		T15	2
auto[1]	values[4]	valids[0x1]	213	1			T11	5		T15	2		T16	1
auto[1]	values[5]	valids[0x0]	310	1			T11	5		T15	3		T16	1
auto[1]	values[5]	valids[0x1]	242	1			T11	1		T15	4		T19	2
auto[1]	values[6]	valids[0x0]	290	1			T11	8		T15	1		T16	2
auto[1]	values[6]	valids[0x1]	187	1			T11	5		T15	1		T19	1
auto[1]	values[7]	valids[0x0]	279	1			T11	8		T15	2		T19	3
auto[1]	values[7]	valids[0x1]	205	1			T11	4		T15	3		T19	2
auto[1]	values[8]	valids[0x0]	2087	1			T1	1		T11	38		T15	8
auto[1]	values[8]	valids[0x1]	1477	1			T11	31		T15	4		T39	2