Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2960571

1

T1

125

T2

1

T4

739

auto[1]

16912

1

T4

3

T11

139

T15

174

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

928547

1

T1

125

T2

1

T4

12

auto[1]

2048936

1

T4

730

T8

666

T11

16319

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	609686	1			T1	118		T2	1		T8	1062
auto[524288:1048575]	309561	1			T1	7		T8	147		T10	49
auto[1048576:1572863]	354822	1			T8	565		T11	464		T15	336
auto[1572864:2097151]	341755	1			T8	988		T11	2801		T15	17
auto[2097152:2621439]	372715	1			T4	2		T8	1074		T11	139
auto[2621440:3145727]	333434	1			T4	333		T8	849		T10	274
auto[3145728:3670015]	328404	1			T8	1308		T11	3587		T14	5
auto[3670016:4194303]	327106	1			T4	407		T8	1451		T11	10

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2066053

1

T1

7

T2

1

T4

742

auto[1]

911430

1

T1

118

T8

6561

T10

414

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2610735

1

T1

125

T2

1

T4

742

auto[1]

366748

1

T11

3834

T14

3

T15

55

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	202359	1			T1	118		T2	1		T8	733
auto[0]	auto[0]	auto[0:524287]	auto[1]	347325	1			T8	329		T11	4865		T15	1169
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	111246	1			T1	7		T8	147		T10	49
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	158457	1			T11	985		T15	100		T31	2879
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	91400	1			T8	565		T11	8		T15	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	213739	1			T11	1		T15	258		T16	137
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	112242	1			T8	652		T11	16		T15	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	183562	1			T8	336		T11	2248		T15	9
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	123006	1			T4	2		T8	1074		T11	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	186368	1			T15	3066		T39	2		T31	265
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	103742	1			T4	3		T8	848		T10	274
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	196919	1			T4	330		T8	1		T11	771
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	76822	1			T8	1308		T11	7		T14	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	202848	1			T11	3576		T15	256		T16	128
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	100202	1			T4	6		T8	1451		T11	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	186458	1			T4	398		T11	1		T31	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	270	1			T15	1		T19	5		T160	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	56818	1			T11	128		T19	640		T28	3075
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	206	1			T11	9		T14	3		T19	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	37742	1			T11	2526		T19	257		T36	873
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	252	1			T11	1		T160	1		T27	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	47416	1			T11	448		T27	1130		T28	2706
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2133	1			T11	4		T16	2		T19	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	41648	1			T11	513		T16	1		T19	1496
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	340	1			T11	2		T39	2		T27	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	60505	1			T11	133		T39	1575		T27	128
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1477	1			T11	4		T15	2		T19	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	29398	1			T15	1		T16	128		T19	2257
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	892	1			T27	1		T28	2		T34	6
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	46012	1			T34	1936		T35	258		T89	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	290	1			T11	1		T16	4		T27	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	38477	1			T11	1		T16	1		T34	2334
auto[1]	auto[0]	auto[0:524287]	auto[0]	232	1			T11	2		T16	2		T27	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	2364	1			T11	26		T27	93		T28	5
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	141	1			T11	2		T15	2		T27	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1388	1			T11	16		T15	45		T27	64
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	153	1			T11	1		T15	2		T27	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1502	1			T11	5		T15	71		T27	42
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	188	1			T11	3		T15	1		T39	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1597	1			T11	8		T15	2		T39	6
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	178	1			T19	1		T27	5		T28	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1930	1			T27	124		T28	1		T34	33
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	144	1			T11	1		T19	5		T27	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1256	1			T11	3		T19	34		T27	12
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	161	1			T11	1		T27	1		T34	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1394	1			T11	3		T27	3		T34	13
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	150	1			T4	1		T11	1		T27	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1262	1			T4	2		T11	3		T27	37
auto[1]	auto[1]	auto[0:524287]	auto[0]	42	1			T55	2		T36	2		T245	3
auto[1]	auto[1]	auto[0:524287]	auto[1]	276	1			T55	3		T245	7		T162	4
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	31	1			T11	2		T19	1		T244	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	350	1			T11	51		T19	6		T244	10
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	51	1			T27	1		T36	1		T38	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	309	1			T27	4		T36	1		T279	23
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	41	1			T11	1		T16	1		T36	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	344	1			T11	8		T16	6		T36	17
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	40	1			T11	1		T35	1		T36	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	348	1			T35	24		T36	1		T135	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	41	1			T15	1		T34	1		T36	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	457	1			T15	50		T34	18		T36	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	37	1			T34	2		T35	2		T89	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	238	1			T34	9		T35	27		T89	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	38	1			T11	1		T16	1		T71	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	229	1			T16	1		T71	32		T41	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1689607	1			T1	7		T2	1		T4	739
auto[0]	auto[0]	auto[1]	907088	1			T1	118		T8	6561		T10	414
auto[0]	auto[1]	auto[0]	359838	1			T11	3769		T14	2		T15	4
auto[0]	auto[1]	auto[1]	4038	1			T11	1		T14	1		T35	2
auto[1]	auto[0]	auto[0]	13797	1			T4	3		T11	70		T15	123
auto[1]	auto[0]	auto[1]	243	1			T11	5		T39	1		T27	5
auto[1]	auto[1]	auto[0]	2811	1			T11	64		T15	51		T16	9
auto[1]	auto[1]	auto[1]	61	1			T36	3		T77	1		T41	4