Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16194

1

T4

14

T8

4

T10

6

auto[1]

11002

1

T2

22

T4

29

T11

47

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4027	1			T4	43		T11	40		T27	309
values[1]	3434	1			T10	6		T27	176		T173	12
values[2]	3340	1			T8	4		T29	16		T32	8
values[3]	3342	1			T30	14		T27	61		T157	4
values[4]	3828	1			T14	4		T28	27		T105	20
values[5]	3392	1			T11	28		T27	20		T28	78
values[6]	2700	1			T2	22		T11	20		T159	14
values[7]	3133	1			T31	24		T104	16		T27	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3899	1			T31	24		T104	16		T27	147
values[1]	3222	1			T11	20		T160	8		T27	49
values[2]	3587	1			T11	28		T159	14		T27	128
values[3]	3417	1			T2	22		T8	4		T14	4
values[4]	3594	1			T4	20		T10	6		T29	16
values[5]	3280	1			T92	2		T27	218		T34	40
values[6]	3067	1			T27	20		T157	4		T28	20
values[7]	3130	1			T4	23		T11	40		T30	14

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	430	1			T27	22		T33	14		T28	14
auto[0]	values[0]	values[1]	247	1			T28	28		T91	4		T41	15
auto[0]	values[0]	values[2]	229	1			T41	15		T161	6		T179	14
auto[0]	values[0]	values[3]	358	1			T27	179		T41	14		T169	14
auto[0]	values[0]	values[4]	455	1			T4	4		T114	4		T35	12
auto[0]	values[0]	values[5]	232	1			T27	29		T34	14		T35	38
auto[0]	values[0]	values[6]	176	1			T27	13		T34	10		T38	15
auto[0]	values[0]	values[7]	220	1			T4	10		T11	21		T27	8
auto[0]	values[1]	values[0]	121	1			T38	27		T52	4		T218	11
auto[0]	values[1]	values[1]	167	1			T173	12		T165	15		T195	10
auto[0]	values[1]	values[2]	240	1			T176	8		T37	8		T172	13
auto[0]	values[1]	values[3]	132	1			T35	12		T38	14		T210	12
auto[0]	values[1]	values[4]	479	1			T10	6		T36	13		T165	4
auto[0]	values[1]	values[5]	376	1			T27	167		T180	19		T195	12
auto[0]	values[1]	values[6]	217	1			T37	34		T41	17		T198	4
auto[0]	values[1]	values[7]	196	1			T195	24		T241	12		T219	12
auto[0]	values[2]	values[0]	167	1			T27	33		T192	22		T133	10
auto[0]	values[2]	values[1]	269	1			T38	17		T180	50		T199	4
auto[0]	values[2]	values[2]	179	1			T27	16		T38	8		T71	11
auto[0]	values[2]	values[3]	427	1			T8	4		T32	8		T172	6
auto[0]	values[2]	values[4]	291	1			T172	9		T41	14		T280	12
auto[0]	values[2]	values[5]	324	1			T37	11		T172	20		T137	52
auto[0]	values[2]	values[6]	314	1			T28	12		T165	18		T38	11
auto[0]	values[2]	values[7]	50	1			T106	8		T210	11		T197	13
auto[0]	values[3]	values[0]	274	1			T27	31		T28	11		T34	12
auto[0]	values[3]	values[1]	274	1			T27	8		T28	11		T34	13
auto[0]	values[3]	values[2]	115	1			T182	2		T180	13		T281	4
auto[0]	values[3]	values[3]	270	1			T191	12		T137	10		T184	2
auto[0]	values[3]	values[4]	274	1			T28	14		T35	9		T41	30
auto[0]	values[3]	values[5]	172	1			T50	2		T137	18		T179	12
auto[0]	values[3]	values[6]	94	1			T157	4		T41	15		T179	9
auto[0]	values[3]	values[7]	397	1			T164	22		T38	9		T137	13
auto[0]	values[4]	values[0]	152	1			T28	9		T36	7		T165	13
auto[0]	values[4]	values[1]	247	1			T105	14		T38	10		T282	4
auto[0]	values[4]	values[2]	230	1			T35	28		T181	22		T37	7
auto[0]	values[4]	values[3]	258	1			T14	4		T186	11		T139	8
auto[0]	values[4]	values[4]	352	1			T166	2		T37	28		T162	13
auto[0]	values[4]	values[5]	236	1			T194	8		T283	2		T284	2
auto[0]	values[4]	values[6]	680	1			T71	12		T54	11		T285	6
auto[0]	values[4]	values[7]	270	1			T165	14		T37	15		T71	31
auto[0]	values[5]	values[0]	397	1			T27	13		T28	10		T183	14
auto[0]	values[5]	values[1]	327	1			T28	14		T37	7		T71	7
auto[0]	values[5]	values[2]	206	1			T11	10		T34	14		T35	7
auto[0]	values[5]	values[3]	215	1			T34	34		T41	29		T286	8
auto[0]	values[5]	values[4]	202	1			T35	13		T71	9		T41	21
auto[0]	values[5]	values[5]	83	1			T38	15		T287	14		T241	12
auto[0]	values[5]	values[6]	206	1			T36	12		T288	6		T83	8
auto[0]	values[5]	values[7]	187	1			T71	15		T289	10		T162	62
auto[0]	values[6]	values[0]	333	1			T137	12		T163	58		T290	12
auto[0]	values[6]	values[1]	110	1			T11	10		T160	8		T27	7
auto[0]	values[6]	values[2]	71	1			T159	14		T27	8		T36	10
auto[0]	values[6]	values[3]	247	1			T41	17		T178	12		T137	16
auto[0]	values[6]	values[4]	116	1			T165	11		T41	19		T137	13
auto[0]	values[6]	values[5]	270	1			T35	8		T163	110		T186	9
auto[0]	values[6]	values[6]	201	1			T165	13		T54	9		T191	11
auto[0]	values[6]	values[7]	279	1			T172	14		T41	12		T162	29
auto[0]	values[7]	values[0]	284	1			T31	24		T104	16		T36	14
auto[0]	values[7]	values[1]	206	1			T34	90		T35	9		T219	14
auto[0]	values[7]	values[2]	545	1			T27	16		T28	53		T37	11
auto[0]	values[7]	values[3]	232	1			T291	2		T271	22		T140	73
auto[0]	values[7]	values[4]	186	1			T27	13		T28	10		T190	6
auto[0]	values[7]	values[5]	231	1			T34	14		T90	18		T38	12
auto[0]	values[7]	values[6]	237	1			T34	10		T292	10		T202	24
auto[0]	values[7]	values[7]	232	1			T28	11		T35	11		T37	11
auto[1]	values[0]	values[0]	297	1			T27	18		T28	6		T35	6
auto[1]	values[0]	values[1]	186	1			T28	16		T41	5		T54	9
auto[1]	values[0]	values[2]	173	1			T41	7		T179	8		T219	67
auto[1]	values[0]	values[3]	169	1			T27	8		T41	6		T169	6
auto[1]	values[0]	values[4]	344	1			T4	16		T35	11		T71	50
auto[1]	values[0]	values[5]	192	1			T27	13		T34	6		T35	9
auto[1]	values[0]	values[6]	97	1			T27	7		T34	39		T38	6
auto[1]	values[0]	values[7]	222	1			T4	13		T11	19		T27	12
auto[1]	values[1]	values[0]	235	1			T38	16		T293	4		T218	136
auto[1]	values[1]	values[1]	83	1			T165	5		T195	13		T162	8
auto[1]	values[1]	values[2]	272	1			T37	12		T172	7		T54	7
auto[1]	values[1]	values[3]	183	1			T35	8		T38	6		T210	14
auto[1]	values[1]	values[4]	202	1			T36	7		T165	18		T180	10
auto[1]	values[1]	values[5]	185	1			T27	9		T180	6		T195	8
auto[1]	values[1]	values[6]	180	1			T37	6		T41	3		T188	38
auto[1]	values[1]	values[7]	166	1			T195	13		T241	11		T294	20
auto[1]	values[2]	values[0]	122	1			T27	13		T41	12		T179	13
auto[1]	values[2]	values[1]	160	1			T38	5		T180	9		T210	41
auto[1]	values[2]	values[2]	299	1			T27	14		T38	12		T71	26
auto[1]	values[2]	values[3]	208	1			T172	14		T163	16		T139	10
auto[1]	values[2]	values[4]	139	1			T29	16		T172	13		T41	6
auto[1]	values[2]	values[5]	202	1			T92	2		T37	9		T172	5
auto[1]	values[2]	values[6]	137	1			T28	8		T165	2		T38	9
auto[1]	values[2]	values[7]	52	1			T210	32		T197	18		T220	2
auto[1]	values[3]	values[0]	306	1			T27	10		T28	13		T34	8
auto[1]	values[3]	values[1]	297	1			T27	12		T28	9		T34	7
auto[1]	values[3]	values[2]	108	1			T180	7		T219	5		T214	12
auto[1]	values[3]	values[3]	181	1			T191	8		T137	10		T195	19
auto[1]	values[3]	values[4]	106	1			T28	6		T35	11		T41	15
auto[1]	values[3]	values[5]	227	1			T137	2		T179	42		T241	90
auto[1]	values[3]	values[6]	50	1			T41	6		T179	15		T295	16
auto[1]	values[3]	values[7]	197	1			T30	14		T38	17		T137	54
auto[1]	values[4]	values[0]	147	1			T28	18		T36	21		T165	7
auto[1]	values[4]	values[1]	178	1			T105	6		T38	10		T163	6
auto[1]	values[4]	values[2]	356	1			T35	8		T37	43		T38	30
auto[1]	values[4]	values[3]	101	1			T186	9		T139	12		T212	58
auto[1]	values[4]	values[4]	119	1			T37	5		T162	7		T186	13
auto[1]	values[4]	values[5]	165	1			T163	7		T197	7		T296	26
auto[1]	values[4]	values[6]	154	1			T71	8		T54	10		T191	10
auto[1]	values[4]	values[7]	183	1			T165	10		T37	5		T71	6
auto[1]	values[5]	values[0]	294	1			T27	7		T28	48		T55	14
auto[1]	values[5]	values[1]	190	1			T28	6		T37	17		T71	13
auto[1]	values[5]	values[2]	382	1			T11	18		T34	6		T35	13
auto[1]	values[5]	values[3]	221	1			T34	47		T41	11		T162	15
auto[1]	values[5]	values[4]	119	1			T35	7		T71	11		T41	19
auto[1]	values[5]	values[5]	122	1			T38	5		T241	89		T263	5
auto[1]	values[5]	values[6]	105	1			T36	12		T83	17		T140	9
auto[1]	values[5]	values[7]	136	1			T71	5		T162	9		T263	46
auto[1]	values[6]	values[0]	216	1			T137	10		T297	4		T163	14
auto[1]	values[6]	values[1]	109	1			T11	10		T27	22		T172	7
auto[1]	values[6]	values[2]	90	1			T27	70		T36	15		T211	5
auto[1]	values[6]	values[3]	152	1			T2	22		T41	6		T137	4
auto[1]	values[6]	values[4]	85	1			T165	9		T41	8		T137	7
auto[1]	values[6]	values[5]	175	1			T35	12		T163	15		T186	11
auto[1]	values[6]	values[6]	160	1			T165	10		T54	15		T191	16
auto[1]	values[6]	values[7]	86	1			T172	8		T41	12		T162	2
auto[1]	values[7]	values[0]	124	1			T36	13		T54	8		T137	23
auto[1]	values[7]	values[1]	172	1			T34	4		T35	87		T298	6
auto[1]	values[7]	values[2]	92	1			T27	4		T28	24		T37	9
auto[1]	values[7]	values[3]	63	1			T140	8		T174	6		T214	11
auto[1]	values[7]	values[4]	125	1			T27	7		T28	10		T163	10
auto[1]	values[7]	values[5]	88	1			T34	6		T38	13		T137	9
auto[1]	values[7]	values[6]	59	1			T34	10		T162	11		T214	5
auto[1]	values[7]	values[7]	257	1			T28	10		T35	9		T37	9