Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	312	1			T4	2		T11	1		T27	5
auto[ReadAddrCrossIntoMailbox]	260	1			T4	1		T11	3		T159	6
auto[ReadAddrCrossOutOfMailbox]	278	1			T11	1		T27	2		T28	1
auto[ReadAddrCrossAllMailbox]	194	1			T4	1		T11	1		T159	4
auto[ReadAddrOutsideMailbox]	3065	1			T2	6		T4	10		T11	10

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2038

1

T2

3

T4

5

T11

14

auto[1]

2071

1

T2

3

T4

9

T11

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	687	1			T4	2		T29	4		T27	12
read_ops[0x0b]	707	1			T4	3		T11	9		T29	2
read_ops[0x3b]	684	1			T2	4		T4	1		T11	1
read_ops[0x6b]	673	1			T4	6		T11	2		T159	4
read_ops[0xbb]	666	1			T4	2		T11	3		T29	2
read_ops[0xeb]	692	1			T2	2		T11	1		T29	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T28	1		T34	3		T204	3
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T204	3		T289	3		T282	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T37	1		T71	1		T180	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	13	1			T180	2		T162	1		T263	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T34	1		T35	2		T37	5
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T34	1		T205	1		T54	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T205	1		T202	2		T180	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T205	1		T202	2		T174	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	243	1			T29	2		T27	4		T28	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	283	1			T4	2		T29	2		T27	8
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T4	1		T91	2		T54	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T27	1		T34	1		T91	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T4	1		T11	1		T159	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T159	2		T27	1		T28	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T11	1		T38	1		T54	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T34	1		T35	1		T165	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T4	1		T159	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T159	1		T27	1		T36	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	249	1			T11	7		T29	1		T27	5
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	269	1			T29	1		T27	3		T157	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T27	1		T204	2		T37	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	19	1			T204	2		T71	1		T201	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T105	2		T205	1		T202	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T28	1		T35	1		T172	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T34	1		T35	1		T38	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T37	1		T205	1		T202	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T11	1		T28	1		T105	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T28	1		T36	1		T38	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	266	1			T2	2		T27	4		T33	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	251	1			T2	2		T4	1		T27	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T4	1		T27	2		T37	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T172	2		T71	1		T180	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T137	1		T180	1		T162	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T28	1		T34	1		T37	3
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T27	1		T28	1		T105	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T36	1		T37	1		T182	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T27	1		T34	1		T169	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T34	1		T41	1		T162	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	236	1			T4	1		T11	1		T159	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	271	1			T4	4		T11	1		T159	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	18	1			T34	1		T37	2		T38	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T28	1		T38	1		T180	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T11	2		T159	1		T36	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T159	1		T28	1		T35	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T38	2		T205	1		T180	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T27	1		T38	1		T205	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T159	1		T27	1		T36	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T159	1		T34	1		T37	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	267	1			T11	1		T29	1		T27	13
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	221	1			T4	2		T29	1		T27	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T27	1		T34	3		T35	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T11	1		T28	1		T36	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T36	1		T37	1		T137	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T28	1		T38	2		T71	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T34	2		T35	1		T185	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T36	1		T185	1		T202	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T27	2		T34	1		T185	3
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T185	3		T202	1		T196	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	246	1			T2	1		T29	1		T30	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	263	1			T2	1		T29	1		T30	1