Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2411840	1			T1	2		T2	1		T3	1
all_pins[1]	2411840	1			T1	2		T2	1		T3	1
all_pins[2]	2411840	1			T1	2		T2	1		T3	1
all_pins[3]	2411840	1			T1	2		T2	1		T3	1
all_pins[4]	2411840	1			T1	2		T2	1		T3	1
all_pins[5]	2411840	1			T1	2		T2	1		T3	1
all_pins[6]	2411840	1			T1	2		T2	1		T3	1
all_pins[7]	2411840	1			T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19278300	1			T1	16		T2	8		T3	8
values[0x1]	16420	1			T11	38		T27	346		T34	7
transitions[0x0=>0x1]	15941	1			T11	31		T27	344		T34	4
transitions[0x1=>0x0]	15956	1			T11	31		T27	344		T34	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2411476	1			T1	2		T2	1		T3	1
all_pins[0]	values[0x1]	364	1			T11	7		T27	85		T55	1
all_pins[0]	transitions[0x0=>0x1]	320	1			T11	6		T27	85		T55	1
all_pins[0]	transitions[0x1=>0x0]	148	1			T11	3		T27	3		T34	1
all_pins[1]	values[0x0]	2411648	1			T1	2		T2	1		T3	1
all_pins[1]	values[0x1]	192	1			T11	4		T27	3		T34	1
all_pins[1]	transitions[0x0=>0x1]	137	1			T11	2		T27	2		T34	1
all_pins[1]	transitions[0x1=>0x0]	209	1			T11	5		T27	6		T36	1
all_pins[2]	values[0x0]	2411576	1			T1	2		T2	1		T3	1
all_pins[2]	values[0x1]	264	1			T11	7		T27	7		T36	2
all_pins[2]	transitions[0x0=>0x1]	224	1			T11	7		T27	7		T36	2
all_pins[2]	transitions[0x1=>0x0]	144	1			T11	2		T55	2		T36	2
all_pins[3]	values[0x0]	2411656	1			T1	2		T2	1		T3	1
all_pins[3]	values[0x1]	184	1			T11	2		T55	2		T36	2
all_pins[3]	transitions[0x0=>0x1]	137	1			T11	2		T55	2		T36	2
all_pins[3]	transitions[0x1=>0x0]	147	1			T11	4		T36	1		T154	1
all_pins[4]	values[0x0]	2411646	1			T1	2		T2	1		T3	1
all_pins[4]	values[0x1]	194	1			T11	4		T36	1		T154	4
all_pins[4]	transitions[0x0=>0x1]	149	1			T11	4		T36	1		T154	3
all_pins[4]	transitions[0x1=>0x0]	882	1			T11	4		T27	249		T34	2
all_pins[5]	values[0x0]	2410913	1			T1	2		T2	1		T3	1
all_pins[5]	values[0x1]	927	1			T11	4		T27	249		T34	2
all_pins[5]	transitions[0x0=>0x1]	791	1			T11	2		T27	249		T34	1
all_pins[5]	transitions[0x1=>0x0]	13964	1			T11	7		T27	1		T34	1
all_pins[6]	values[0x0]	2397740	1			T1	2		T2	1		T3	1
all_pins[6]	values[0x1]	14100	1			T11	9		T27	1		T34	2
all_pins[6]	transitions[0x0=>0x1]	14048	1			T11	8		T36	3		T158	1
all_pins[6]	transitions[0x1=>0x0]	143	1			T36	1		T154	2		T77	1
all_pins[7]	values[0x0]	2411645	1			T1	2		T2	1		T3	1
all_pins[7]	values[0x1]	195	1			T11	1		T27	1		T34	2
all_pins[7]	transitions[0x0=>0x1]	135	1			T27	1		T34	2		T154	2
all_pins[7]	transitions[0x1=>0x0]	319	1			T11	6		T27	85		T55	1