Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.26	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	4	124	96.88

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	4	124	96.88	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4182	1			T4	20		T27	176		T28	24
values[1]	3378	1			T159	14		T160	8		T27	70
values[2]	3838	1			T4	23		T10	6		T14	4
values[3]	3165	1			T11	20		T32	8		T27	247
values[4]	3404	1			T2	22		T8	4		T11	20
values[5]	3248	1			T92	2		T104	16		T27	76
values[6]	3306	1			T29	16		T27	62		T28	85
values[7]	2675	1			T11	48		T31	24		T27	138

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3589	1			T2	22		T4	43		T28	45
values[1]	3521	1			T92	2		T27	294		T28	24
values[2]	3608	1			T8	4		T11	68		T29	16
values[3]	3982	1			T11	20		T32	8		T104	16
values[4]	3030	1			T14	4		T159	14		T30	14
values[5]	3563	1			T10	6		T27	82		T28	52
values[6]	3043	1			T157	4		T28	65		T34	114
values[7]	2860	1			T31	24		T27	20		T33	14

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26775

1

T2

22

T4

42

T8

4

auto[1]

421

1

T4

1

T11

3

T29

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	4	124	96.88	4

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[4]]	[values[7]]	0	1	1
[auto[1]]	[values[6]]	[values[1]]	0	1	1
[auto[1]]	[values[7]]	[values[0]]	0	1	1
[auto[1]]	[values[7]]	[values[4]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	678	1			T4	20		T71	77		T161	6
auto[0]	values[0]	values[1]	653	1			T38	24		T41	20		T137	123
auto[0]	values[0]	values[2]	327	1			T38	20		T162	18		T163	33
auto[0]	values[0]	values[3]	555	1			T114	4		T164	22		T165	20
auto[0]	values[0]	values[4]	681	1			T27	174		T105	20		T41	27
auto[0]	values[0]	values[5]	499	1			T166	2		T167	16		T168	20
auto[0]	values[0]	values[6]	358	1			T28	24		T38	20		T41	46
auto[0]	values[0]	values[7]	369	1			T34	20		T35	20		T38	22
auto[0]	values[1]	values[0]	251	1			T38	20		T41	22		T169	20
auto[0]	values[1]	values[1]	667	1			T27	41		T35	95		T91	4
auto[0]	values[1]	values[2]	371	1			T160	8		T34	20		T35	45
auto[0]	values[1]	values[3]	488	1			T37	20		T170	8		T171	14
auto[0]	values[1]	values[4]	288	1			T159	14		T27	28		T172	18
auto[0]	values[1]	values[5]	623	1			T34	38		T173	12		T55	25
auto[0]	values[1]	values[6]	249	1			T165	20		T71	20		T41	20
auto[0]	values[1]	values[7]	384	1			T41	20		T174	29		T175	22
auto[0]	values[2]	values[0]	405	1			T4	22		T176	8		T177	4
auto[0]	values[2]	values[1]	334	1			T178	12		T179	20		T180	20
auto[0]	values[2]	values[2]	649	1			T28	20		T36	24		T37	20
auto[0]	values[2]	values[3]	494	1			T34	20		T37	20		T71	20
auto[0]	values[2]	values[4]	291	1			T14	4		T162	19		T163	39
auto[0]	values[2]	values[5]	618	1			T10	6		T35	23		T36	20
auto[0]	values[2]	values[6]	617	1			T28	41		T34	94		T181	22
auto[0]	values[2]	values[7]	372	1			T33	14		T35	20		T182	2
auto[0]	values[3]	values[0]	562	1			T38	23		T71	55		T41	21
auto[0]	values[3]	values[1]	518	1			T27	206		T183	14		T38	20
auto[0]	values[3]	values[2]	463	1			T28	40		T35	20		T184	2
auto[0]	values[3]	values[3]	434	1			T11	20		T32	8		T185	12
auto[0]	values[3]	values[4]	457	1			T27	20		T28	20		T36	28
auto[0]	values[3]	values[5]	201	1			T186	20		T187	24		T188	20
auto[0]	values[3]	values[6]	204	1			T34	20		T37	20		T54	23
auto[0]	values[3]	values[7]	283	1			T27	20		T36	26		T189	10
auto[0]	values[4]	values[0]	598	1			T2	22		T28	45		T35	75
auto[0]	values[4]	values[1]	423	1			T28	22		T106	8		T190	6
auto[0]	values[4]	values[2]	584	1			T8	4		T11	18		T38	20
auto[0]	values[4]	values[3]	317	1			T27	20		T52	4		T191	20
auto[0]	values[4]	values[4]	243	1			T30	12		T192	22		T191	20
auto[0]	values[4]	values[5]	330	1			T35	20		T172	19		T71	20
auto[0]	values[4]	values[6]	540	1			T35	139		T172	22		T193	56
auto[0]	values[4]	values[7]	323	1			T28	20		T35	20		T194	8
auto[0]	values[5]	values[0]	526	1			T41	23		T180	20		T195	122
auto[0]	values[5]	values[1]	448	1			T92	2		T27	44		T35	20
auto[0]	values[5]	values[2]	416	1			T196	4		T186	111		T197	64
auto[0]	values[5]	values[3]	516	1			T104	16		T27	30		T35	36
auto[0]	values[5]	values[4]	268	1			T36	27		T54	20		T137	22
auto[0]	values[5]	values[5]	420	1			T71	20		T180	36		T198	4
auto[0]	values[5]	values[6]	293	1			T157	4		T36	42		T37	39
auto[0]	values[5]	values[7]	299	1			T41	22		T199	4		T195	21
auto[0]	values[6]	values[0]	358	1			T41	40		T47	16		T200	2
auto[0]	values[6]	values[1]	243	1			T34	20		T165	20		T201	6
auto[0]	values[6]	values[2]	243	1			T29	14		T37	44		T195	26
auto[0]	values[6]	values[3]	557	1			T202	24		T180	19		T203	62
auto[0]	values[6]	values[4]	398	1			T27	20		T28	27		T34	47
auto[0]	values[6]	values[5]	455	1			T27	41		T165	20		T172	22
auto[0]	values[6]	values[6]	546	1			T165	23		T204	18		T205	14
auto[0]	values[6]	values[7]	445	1			T28	55		T41	20		T54	23
auto[0]	values[7]	values[0]	158	1			T90	18		T165	22		T187	32
auto[0]	values[7]	values[1]	187	1			T179	24		T206	2		T207	6
auto[0]	values[7]	values[2]	500	1			T11	47		T165	20		T41	45
auto[0]	values[7]	values[3]	558	1			T27	76		T34	37		T53	20
auto[0]	values[7]	values[4]	368	1			T27	20		T172	22		T208	4
auto[0]	values[7]	values[5]	358	1			T27	40		T28	52		T34	43
auto[0]	values[7]	values[6]	182	1			T38	20		T54	21		T209	6
auto[0]	values[7]	values[7]	332	1			T31	24		T172	20		T41	20
auto[1]	values[0]	values[0]	9	1			T71	1		T210	1		T211	2
auto[1]	values[0]	values[1]	7	1			T38	2		T195	2		T212	2
auto[1]	values[0]	values[2]	7	1			T162	2		T163	2		T168	1
auto[1]	values[0]	values[3]	6	1			T38	1		T212	2		T213	3
auto[1]	values[0]	values[4]	8	1			T27	2		T41	2		T180	2
auto[1]	values[0]	values[5]	8	1			T22	1		T214	5		T215	1
auto[1]	values[0]	values[6]	10	1			T41	1		T216	2		T203	2
auto[1]	values[0]	values[7]	7	1			T217	2		T163	2		T175	2
auto[1]	values[1]	values[0]	6	1			T139	2		T218	4		-	-
auto[1]	values[1]	values[1]	4	1			T35	1		T219	1		T220	1
auto[1]	values[1]	values[2]	7	1			T35	2		T71	1		T41	2
auto[1]	values[1]	values[3]	8	1			T139	2		T174	2		T221	2
auto[1]	values[1]	values[4]	6	1			T27	1		T172	2		T54	3
auto[1]	values[1]	values[5]	14	1			T34	2		T37	3		T191	2
auto[1]	values[1]	values[6]	6	1			T168	2		T174	1		T221	1
auto[1]	values[1]	values[7]	6	1			T174	3		T175	1		T211	1
auto[1]	values[2]	values[0]	8	1			T4	1		T186	1		T139	1
auto[1]	values[2]	values[1]	5	1			T162	1		T141	1		T222	1
auto[1]	values[2]	values[2]	9	1			T71	1		T180	3		T223	1
auto[1]	values[2]	values[3]	9	1			T137	1		T224	2		T225	2
auto[1]	values[2]	values[4]	5	1			T162	2		T163	1		T226	1
auto[1]	values[2]	values[5]	9	1			T162	1		T186	2		T224	3
auto[1]	values[2]	values[6]	5	1			T38	2		T172	2		T227	1
auto[1]	values[2]	values[7]	8	1			T168	2		T228	2		T224	1
auto[1]	values[3]	values[0]	6	1			T71	2		T218	2		T83	2
auto[1]	values[3]	values[1]	7	1			T27	1		T139	3		T22	1
auto[1]	values[3]	values[2]	6	1			T195	3		T168	1		T221	1
auto[1]	values[3]	values[3]	7	1			T180	2		T162	2		T219	1
auto[1]	values[3]	values[4]	4	1			T229	1		T84	1		T230	2
auto[1]	values[3]	values[5]	4	1			T187	2		T220	1		T231	1
auto[1]	values[3]	values[6]	4	1			T54	1		T180	1		T188	2
auto[1]	values[3]	values[7]	5	1			T197	1		T232	3		T222	1
auto[1]	values[4]	values[0]	11	1			T35	1		T195	1		T233	2
auto[1]	values[4]	values[1]	7	1			T28	2		T38	2		T139	1
auto[1]	values[4]	values[2]	8	1			T11	2		T140	1		T234	1
auto[1]	values[4]	values[3]	2	1			T219	1		T234	1		-	-
auto[1]	values[4]	values[4]	4	1			T30	2		T212	2		-	-
auto[1]	values[4]	values[5]	4	1			T172	1		T224	2		T231	1
auto[1]	values[4]	values[6]	10	1			T35	4		T163	3		T235	1
auto[1]	values[5]	values[0]	7	1			T41	1		T234	2		T84	2
auto[1]	values[5]	values[1]	13	1			T27	2		T165	2		T172	3
auto[1]	values[5]	values[2]	6	1			T186	2		T197	1		T83	1
auto[1]	values[5]	values[3]	13	1			T37	5		T210	1		T162	1
auto[1]	values[5]	values[4]	3	1			T175	3		-	-		-	-
auto[1]	values[5]	values[5]	2	1			T180	1		T236	1		-	-
auto[1]	values[5]	values[6]	7	1			T36	3		T37	1		T163	2
auto[1]	values[5]	values[7]	11	1			T41	2		T197	1		T84	2
auto[1]	values[6]	values[0]	6	1			T22	1		T237	2		T84	1
auto[1]	values[6]	values[2]	10	1			T29	2		T37	6		T238	2
auto[1]	values[6]	values[3]	7	1			T180	1		T203	1		T239	1
auto[1]	values[6]	values[4]	6	1			T34	2		T35	1		T162	1
auto[1]	values[6]	values[5]	16	1			T27	1		T240	6		T221	1
auto[1]	values[6]	values[6]	7	1			T195	2		T241	1		T163	2
auto[1]	values[6]	values[7]	9	1			T28	3		T54	1		T191	1
auto[1]	values[7]	values[1]	5	1			T141	1		T175	1		T231	3
auto[1]	values[7]	values[2]	2	1			T11	1		T229	1		-	-
auto[1]	values[7]	values[3]	11	1			T27	2		T218	1		T83	2
auto[1]	values[7]	values[5]	2	1			T34	1		T179	1		-	-
auto[1]	values[7]	values[6]	5	1			T242	1		T243	4		-	-
auto[1]	values[7]	values[7]	7	1			T186	5		T168	2		-	-