Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1840

1

T4

9

T5

2

T6

4

auto[1]

1805

1

T4

20

T5

1

T6

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2080

1

T4

29

T5

3

T11

28

auto[1]

1565

1

T6

7

T11

10

T15

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2838

1

T4

20

T5

1

T6

7

auto[1]

807

1

T4

9

T5

2

T11

13

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	721	1			T4	3		T5	1		T6	2
valid[1]	687	1			T4	8		T5	1		T6	1
valid[2]	751	1			T4	9		T6	2		T11	8
valid[3]	756	1			T4	2		T5	1		T6	1
valid[4]	730	1			T4	7		T6	1		T11	9

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	127	1			T4	2		T11	1		T19	1
auto[0]	auto[0]	valid[0]	auto[1]	158	1			T6	1		T11	2		T17	1
auto[0]	auto[0]	valid[1]	auto[0]	145	1			T4	2		T5	1		T11	2
auto[0]	auto[0]	valid[1]	auto[1]	166	1			T11	1		T81	5		T320	2
auto[0]	auto[0]	valid[2]	auto[0]	130	1			T4	1		T16	1		T105	1
auto[0]	auto[0]	valid[2]	auto[1]	153	1			T6	1		T11	2		T17	1
auto[0]	auto[0]	valid[3]	auto[0]	135	1			T11	2		T16	1		T19	1
auto[0]	auto[0]	valid[3]	auto[1]	179	1			T6	1		T11	1		T17	1
auto[0]	auto[0]	valid[4]	auto[0]	127	1			T4	2		T11	3		T19	1
auto[0]	auto[0]	valid[4]	auto[1]	135	1			T6	1		T15	1		T17	1
auto[0]	auto[1]	valid[0]	auto[0]	131	1			T4	1		T11	1		T16	2
auto[0]	auto[1]	valid[0]	auto[1]	137	1			T6	1		T11	1		T81	3
auto[0]	auto[1]	valid[1]	auto[0]	114	1			T4	2		T27	1		T86	1
auto[0]	auto[1]	valid[1]	auto[1]	136	1			T6	1		T11	1		T17	1
auto[0]	auto[1]	valid[2]	auto[0]	135	1			T4	6		T11	3		T19	2
auto[0]	auto[1]	valid[2]	auto[1]	151	1			T6	1		T11	1		T17	1
auto[0]	auto[1]	valid[3]	auto[0]	111	1			T4	2		T11	2		T15	1
auto[0]	auto[1]	valid[3]	auto[1]	169	1			T81	4		T87	1		T128	1
auto[0]	auto[1]	valid[4]	auto[0]	118	1			T4	2		T11	1		T19	2
auto[0]	auto[1]	valid[4]	auto[1]	181	1			T11	1		T15	1		T17	3
auto[1]	auto[0]	valid[0]	auto[0]	78	1			T15	1		T19	2		T87	1
auto[1]	auto[0]	valid[1]	auto[0]	64	1			T4	1		T317	1		T128	2
auto[1]	auto[0]	valid[2]	auto[0]	80	1			T4	1		T19	1		T27	1
auto[1]	auto[0]	valid[3]	auto[0]	81	1			T5	1		T11	2		T19	1
auto[1]	auto[0]	valid[4]	auto[0]	82	1			T11	2		T15	1		T19	1
auto[1]	auto[1]	valid[0]	auto[0]	90	1			T5	1		T19	1		T27	1
auto[1]	auto[1]	valid[1]	auto[0]	62	1			T4	3		T11	2		T19	2
auto[1]	auto[1]	valid[2]	auto[0]	102	1			T4	1		T11	2		T19	1
auto[1]	auto[1]	valid[3]	auto[0]	81	1			T11	3		T27	1		T28	1
auto[1]	auto[1]	valid[4]	auto[0]	87	1			T4	3		T11	2		T27	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal