Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50996

1

T4

475

T5

118

T11

778

auto[1]

16681

1

T6

7

T11

85

T15

23

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49159

1

T4

319

T5

79

T6

7

auto[1]

18518

1

T4

156

T5

39

T11

285

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34792	1			T4	237		T5	66		T6	7
others[1]	5691	1			T4	32		T5	5		T11	68
others[2]	5762	1			T4	47		T5	10		T11	81
others[3]	6475	1			T4	47		T5	7		T11	82
interest[1]	3718	1			T4	34		T5	8		T11	33
interest[4]	22732	1			T4	155		T5	39		T6	7
interest[64]	11239	1			T4	78		T5	22		T11	141

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16637	1			T4	162		T5	44		T11	264
auto[0]	auto[0]	others[1]	2759	1			T4	18		T5	3		T11	34
auto[0]	auto[0]	others[2]	2774	1			T4	34		T5	6		T11	50
auto[0]	auto[0]	others[3]	3172	1			T4	28		T5	7		T11	51
auto[0]	auto[0]	interest[1]	1723	1			T4	22		T5	7		T11	17
auto[0]	auto[0]	interest[4]	10777	1			T4	109		T5	29		T11	179
auto[0]	auto[0]	interest[64]	5413	1			T4	55		T5	12		T11	77
auto[0]	auto[1]	others[0]	8680	1			T6	7		T11	52		T15	12
auto[0]	auto[1]	others[1]	1347	1			T11	7		T15	3		T81	21
auto[0]	auto[1]	others[2]	1422	1			T11	6		T81	49		T28	3
auto[0]	auto[1]	others[3]	1552	1			T11	7		T15	3		T81	51
auto[0]	auto[1]	interest[1]	933	1			T11	3		T81	28		T28	1
auto[0]	auto[1]	interest[4]	5790	1			T6	7		T11	31		T15	5
auto[0]	auto[1]	interest[64]	2747	1			T11	10		T15	5		T81	89
auto[1]	auto[0]	others[0]	9475	1			T4	75		T5	22		T11	142
auto[1]	auto[0]	others[1]	1585	1			T4	14		T5	2		T11	27
auto[1]	auto[0]	others[2]	1566	1			T4	13		T5	4		T11	25
auto[1]	auto[0]	others[3]	1751	1			T4	19		T11	24		T15	6
auto[1]	auto[0]	interest[1]	1062	1			T4	12		T5	1		T11	13
auto[1]	auto[0]	interest[4]	6165	1			T4	46		T5	10		T11	95
auto[1]	auto[0]	interest[64]	3079	1			T4	23		T5	10		T11	54

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal