Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	820	1			T11	20		T27	11		T34	4
all_values[1]	820	1			T11	20		T27	11		T34	4
all_values[2]	820	1			T11	20		T27	11		T34	4
all_values[3]	820	1			T11	20		T27	11		T34	4
all_values[4]	820	1			T11	20		T27	11		T34	4
all_values[5]	820	1			T11	20		T27	11		T34	4
all_values[6]	820	1			T11	20		T27	11		T34	4
all_values[7]	820	1			T11	20		T27	11		T34	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3543

1

T11

99

T27

46

T34

14

auto[1]

3017

1

T11

61

T27

42

T34

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2665

1

T11

56

T27

42

T34

20

auto[1]

3895

1

T11

104

T27

46

T34

12

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3751

1

T11

86

T27

55

T34

23

auto[1]

2809

1

T11

74

T27

33

T34

9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	204	1			T11	2		T27	4		T34	3
all_values[0]	auto[0]	auto[0]	auto[1]	74	1			T11	1		T27	1		T55	2
all_values[0]	auto[0]	auto[1]	auto[0]	114	1			T11	2		T27	2		T34	1
all_values[0]	auto[0]	auto[1]	auto[1]	73	1			T11	4		T27	1		T36	2
all_values[0]	auto[1]	auto[0]	auto[1]	197	1			T11	5		T55	2		T36	2
all_values[0]	auto[1]	auto[1]	auto[1]	158	1			T11	6		T27	3		T36	1
all_values[1]	auto[0]	auto[0]	auto[0]	169	1			T11	5		T27	4		T55	2
all_values[1]	auto[0]	auto[0]	auto[1]	70	1			T11	2		T36	2		T154	1
all_values[1]	auto[0]	auto[1]	auto[0]	142	1			T11	2		T34	2		T55	1
all_values[1]	auto[0]	auto[1]	auto[1]	74	1			T11	1		T27	1		T158	2
all_values[1]	auto[1]	auto[0]	auto[1]	214	1			T11	8		T27	4		T34	1
all_values[1]	auto[1]	auto[1]	auto[1]	151	1			T11	2		T27	2		T34	1
all_values[2]	auto[0]	auto[0]	auto[0]	149	1			T11	3		T34	4		T154	1
all_values[2]	auto[0]	auto[0]	auto[1]	93	1			T11	4		T27	4		T154	3
all_values[2]	auto[0]	auto[1]	auto[0]	135	1			T11	2		T27	1		T55	2
all_values[2]	auto[0]	auto[1]	auto[1]	84	1			T11	4		T27	1		T36	2
all_values[2]	auto[1]	auto[0]	auto[1]	194	1			T11	3		T27	4		T55	1
all_values[2]	auto[1]	auto[1]	auto[1]	165	1			T11	4		T27	1		T55	1
all_values[3]	auto[0]	auto[0]	auto[0]	175	1			T11	10		T27	4		T34	2
all_values[3]	auto[0]	auto[0]	auto[1]	74	1			T11	2		T27	1		T36	1
all_values[3]	auto[0]	auto[1]	auto[0]	156	1			T11	4		T27	4		T34	2
all_values[3]	auto[0]	auto[1]	auto[1]	76	1			T55	1		T36	1		T154	2
all_values[3]	auto[1]	auto[0]	auto[1]	174	1			T11	3		T36	1		T154	3
all_values[3]	auto[1]	auto[1]	auto[1]	165	1			T11	1		T27	2		T55	2
all_values[4]	auto[0]	auto[0]	auto[0]	166	1			T11	2		T27	2		T34	1
all_values[4]	auto[0]	auto[0]	auto[1]	96	1			T11	4		T27	1		T34	1
all_values[4]	auto[0]	auto[1]	auto[0]	142	1			T11	2		T27	3		T55	3
all_values[4]	auto[0]	auto[1]	auto[1]	77	1			T11	1		T154	1		T41	1
all_values[4]	auto[1]	auto[0]	auto[1]	181	1			T11	9		T27	4		T34	2
all_values[4]	auto[1]	auto[1]	auto[1]	158	1			T11	2		T27	1		T36	1
all_values[5]	auto[0]	auto[0]	auto[0]	266	1			T11	8		T27	1		T36	2
all_values[5]	auto[0]	auto[1]	auto[0]	214	1			T11	3		T27	7		T34	2
all_values[5]	auto[1]	auto[0]	auto[1]	169	1			T11	4		T27	2		T55	1
all_values[5]	auto[1]	auto[1]	auto[1]	171	1			T11	5		T27	1		T34	2
all_values[6]	auto[0]	auto[0]	auto[0]	173	1			T11	5		T27	6		T55	3
all_values[6]	auto[0]	auto[0]	auto[1]	81	1			T11	1		T158	1		T155	1
all_values[6]	auto[0]	auto[1]	auto[0]	154	1			T11	4		T27	1		T34	2
all_values[6]	auto[0]	auto[1]	auto[1]	66	1			T11	3		T27	1		T34	1
all_values[6]	auto[1]	auto[0]	auto[1]	182	1			T11	3		T27	1		T154	4
all_values[6]	auto[1]	auto[1]	auto[1]	164	1			T11	4		T27	2		T34	1
all_values[7]	auto[0]	auto[0]	auto[0]	177	1			T11	1		T27	1		T55	2
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T11	2		T27	1		T36	2
all_values[7]	auto[0]	auto[1]	auto[0]	129	1			T11	1		T27	2		T34	1
all_values[7]	auto[0]	auto[1]	auto[1]	71	1			T11	1		T27	1		T34	1
all_values[7]	auto[1]	auto[0]	auto[1]	188	1			T11	12		T27	1		T55	2
all_values[7]	auto[1]	auto[1]	auto[1]	178	1			T11	3		T27	5		T34	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal