Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2645846	1			T1	1		T2	1		T3	1
all_values[1]	2645846	1			T1	1		T2	1		T3	1
all_values[2]	2645846	1			T1	1		T2	1		T3	1
all_values[3]	2645846	1			T1	1		T2	1		T3	1
all_values[4]	2645846	1			T1	1		T2	1		T3	1
all_values[5]	2645846	1			T1	1		T2	1		T3	1
all_values[6]	2645846	1			T1	1		T2	1		T3	1
all_values[7]	2645846	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20453460

1

T1

8

T2

8

T3

8

auto[1]

713308

1

T18

3636

T47

30

T68

108

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21145344

1

T1

8

T2

8

T3

8

auto[1]

21424

1

T5

2

T6

2

T18

152

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2531105	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	11101	1			T18	71		T21	30		T55	26
all_values[0]	auto[1]	auto[0]	102894	1			T18	4		T68	6		T67	3
all_values[0]	auto[1]	auto[1]	746	1			T47	2		T68	8		T67	3
all_values[1]	auto[0]	auto[0]	2490853	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	5033	1			T18	40		T21	30		T55	10
all_values[1]	auto[1]	auto[0]	149473	1			T18	6		T47	2		T68	3
all_values[1]	auto[1]	auto[1]	487	1			T18	2		T47	4		T68	6
all_values[2]	auto[0]	auto[0]	2594160	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	1867	1			T18	10		T21	1		T31	4
all_values[2]	auto[1]	auto[0]	49560	1			T18	3		T47	1		T68	4
all_values[2]	auto[1]	auto[1]	259	1			T18	4		T47	6		T68	10
all_values[3]	auto[0]	auto[0]	2576724	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	188	1			T47	1		T68	7		T67	1
all_values[3]	auto[1]	auto[0]	68752	1			T18	1795		T47	3		T68	10
all_values[3]	auto[1]	auto[1]	182	1			T18	7		T47	3		T68	5
all_values[4]	auto[0]	auto[0]	2546165	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	185	1			T18	3		T47	2		T68	5
all_values[4]	auto[1]	auto[0]	99332	1			T18	4		T68	4		T67	1
all_values[4]	auto[1]	auto[1]	164	1			T18	2		T47	1		T68	7
all_values[5]	auto[0]	auto[0]	2578941	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	278	1			T5	2		T6	2		T18	3
all_values[5]	auto[1]	auto[0]	66452	1			T18	2		T47	2		T68	9
all_values[5]	auto[1]	auto[1]	175	1			T18	1		T68	6		T67	2
all_values[6]	auto[0]	auto[0]	2537445	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	193	1			T18	1		T47	1		T68	4
all_values[6]	auto[1]	auto[0]	108037	1			T18	1797		T47	1		T68	10
all_values[6]	auto[1]	auto[1]	171	1			T18	5		T47	1		T68	7
all_values[7]	auto[0]	auto[0]	2579031	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	191	1			T18	1		T47	3		T68	6
all_values[7]	auto[1]	auto[0]	66420	1			T18	2		T47	1		T68	6
all_values[7]	auto[1]	auto[1]	204	1			T18	2		T47	3		T68	7