Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	29563	1			T4	417		T10	6		T36	8
auto[SpiFlashAddrCfg]	6027	1			T4	45		T7	1		T13	1
auto[SpiFlashAddr3b]	7611	1			T2	1		T4	61		T7	1
auto[SpiFlashAddr4b]	6054	1			T4	47		T14	2		T15	8

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28536

1

T2

1

T4

382

T7

2

auto[1]

20719

1

T4

188

T15

10

T18

72

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25423

1

T2

1

T4

225

T7

1

auto[1]

23832

1

T4

345

T7

1

T10

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	33362	1			T4	448		T9	6		T10	6
values[1]	847	1			T4	5		T18	2		T28	10
values[2]	1186	1			T4	11		T10	2		T28	1
values[3]	1222	1			T4	3		T74	2		T37	4
values[4]	1128	1			T4	5		T7	1		T17	2
values[5]	1151	1			T4	12		T37	2		T18	11
values[6]	1179	1			T4	7		T36	8		T18	8
values[7]	1168	1			T2	1		T4	12		T18	4
values[8]	8012	1			T4	67		T7	1		T10	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23044

1

T4

570

T9

6

T10

12

auto[1]

26211

1

T2

1

T7

2

T13

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

47502

1

T2

1

T4

554

T7

2

write

1753

1

T4

16

T18

12

T28

13

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16026

1

T2

1

T4

127

T7

2

valids[0x1]

33229

1

T4

443

T9

6

T10

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1272	1			T4	4		T74	2		T18	6
internal_process_ops[0x5a]	1283	1			T4	4		T9	6		T15	2
internal_process_ops[0x05]	18271	1			T4	340		T37	2		T18	43
internal_process_ops[0x35]	1266	1			T4	12		T10	6		T37	2
internal_process_ops[0x15]	1309	1			T4	9		T36	8		T18	7
internal_process_ops[0x03]	796	1			T4	8		T18	2		T28	3
internal_process_ops[0x0b]	810	1			T4	11		T17	2		T18	5
internal_process_ops[0x3b]	879	1			T2	1		T4	8		T7	1
internal_process_ops[0x6b]	817	1			T4	11		T7	1		T10	4
internal_process_ops[0xbb]	875	1			T4	4		T15	4		T17	2
internal_process_ops[0xeb]	885	1			T4	11		T10	2		T13	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48430

1

T2

1

T4

567

T7

2

auto[1]

825

1

T4

3

T18

3

T28

11

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47515

1

T2

1

T4

553

T7

2

auto[1]

1740

1

T4

17

T18

9

T28

13

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8265

1

T4

298

T10

6

T36

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4583

1

T4

111

T31

47

T32

184

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1581

1

T4

25

T17

6

T37

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1370

1

T4

17

T31

21

T32

21

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2029

1

T4

29

T9

6

T10

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1602

1

T4

32

T15

2

T31

14

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1534

1

T4

24

T14

2

T90

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1276

1

T4

18

T15

8

T31

19

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

56

1

T4

1

T31

1

T32

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

51

1

T32

2

T33

3

T38

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

47

1

T4

6

T32

1

T41

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

62

1

T4

1

T31

2

T38

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

58

1

T31

1

T32

4

T67

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

37

1

T4

1

T40

1

T41

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

65

1

T4

1

T31

2

T33

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

49

1

T4

1

T31

1

T38

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

60

1

T53

2

T33

2

T183

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

45

1

T32

2

T184

1

T38

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

47

1

T31

1

T53

2

T38

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

42

1

T32

1

T44

2

T185

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

71

1

T4

4

T33

3

T186

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

34

1

T33

2

T99

1

T42

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

35

1

T4

1

T31

1

T32

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

45

1

T31

1

T32

2

T39

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9582

1

T18

60

T28

127

T21

19

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6692

1

T18

30

T28

180

T21

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1356

1

T7

1

T13

1

T18

19

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1257

1

T18

5

T28

6

T55

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1858

1

T2

1

T7

1

T18

14

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1683

1

T18

14

T28

14

T21

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1449

1

T18

5

T28

5

T21

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1385

1

T18

19

T28

10

T21

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

73

1

T18

4

T28

1

T21

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

53

1

T28

1

T98

1

T92

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

55

1

T47

1

T92

2

T187

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

44

1

T18

1

T47

1

T98

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

50

1

T18

2

T67

4

T188

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

58

1

T18

1

T98

2

T189

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

76

1

T28

1

T55

4

T67

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

70

1

T28

3

T188

1

T190

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

63

1

T67

1

T188

2

T191

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

49

1

T28

3

T188

2

T189

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

70

1

T47

1

T92

3

T192

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

63

1

T18

1

T28

3

T92

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

54

1

T18

1

T21

2

T193

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

70

1

T67

1

T98

3

T192

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

48

1

T18

2

T47

1

T92

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

53

1

T28

1

T98

1

T92

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	2949	1			T4	46		T15	2		T37	2
auto[0]	values[0]	valids[0x1]	11937	1			T4	402		T9	6		T10	6
auto[0]	values[1]	valids[0x1]	377	1			T4	5		T31	6		T32	5
auto[0]	values[2]	valids[0x0]	386	1			T4	8		T10	2		T194	8
auto[0]	values[2]	valids[0x1]	242	1			T4	3		T89	6		T31	5
auto[0]	values[3]	valids[0x0]	404	1			T4	3		T74	2		T37	2
auto[0]	values[3]	valids[0x1]	236	1			T37	2		T31	2		T32	4
auto[0]	values[4]	valids[0x0]	357	1			T4	3		T17	2		T194	4
auto[0]	values[4]	valids[0x1]	188	1			T4	2		T37	2		T31	2
auto[0]	values[5]	valids[0x0]	377	1			T4	12		T89	2		T31	6
auto[0]	values[5]	valids[0x1]	213	1			T37	2		T195	2		T31	4
auto[0]	values[6]	valids[0x0]	396	1			T4	6		T89	4		T31	9
auto[0]	values[6]	valids[0x1]	203	1			T4	1		T36	8		T31	7
auto[0]	values[7]	valids[0x0]	410	1			T4	9		T90	6		T31	9
auto[0]	values[7]	valids[0x1]	209	1			T4	3		T32	8		T53	1
auto[0]	values[8]	valids[0x0]	2708	1			T4	40		T10	4		T14	2
auto[0]	values[8]	valids[0x1]	1452	1			T4	27		T15	2		T17	4
auto[1]	values[0]	valids[0x0]	3753	1			T18	28		T28	28		T21	7
auto[1]	values[0]	valids[0x1]	14723	1			T18	87		T28	298		T21	17
auto[1]	values[1]	valids[0x1]	470	1			T18	2		T28	10		T21	1
auto[1]	values[2]	valids[0x0]	348	1			T28	1		T55	5		T47	6
auto[1]	values[2]	valids[0x1]	210	1			T55	1		T47	5		T67	3
auto[1]	values[3]	valids[0x0]	330	1			T18	5		T21	2		T55	5
auto[1]	values[3]	valids[0x1]	252	1			T18	2		T28	2		T21	3
auto[1]	values[4]	valids[0x0]	361	1			T7	1		T18	2		T28	3
auto[1]	values[4]	valids[0x1]	222	1			T18	2		T28	3		T47	4
auto[1]	values[5]	valids[0x0]	316	1			T18	7		T28	2		T55	1
auto[1]	values[5]	valids[0x1]	245	1			T18	4		T55	2		T47	2
auto[1]	values[6]	valids[0x0]	355	1			T18	4		T28	3		T21	2
auto[1]	values[6]	valids[0x1]	225	1			T18	4		T28	1		T55	2
auto[1]	values[7]	valids[0x0]	342	1			T2	1		T18	3		T136	1
auto[1]	values[7]	valids[0x1]	207	1			T18	1		T28	3		T67	1
auto[1]	values[8]	valids[0x0]	2234	1			T7	1		T13	1		T18	16
auto[1]	values[8]	valids[0x1]	1618	1			T18	11		T28	17		T21	6