Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2982484

1

T2

1

T4

25791

T7

19

auto[1]

16903

1

T4

330

T18

38

T28

252

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1127481

1

T2

1

T4

84

T7

19

auto[1]

1871906

1

T4

26037

T18

7081

T28

4827

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	571657	1			T4	839		T7	5		T9	652
auto[524288:1048575]	396695	1			T4	1598		T9	1397		T13	225
auto[1048576:1572863]	298143	1			T4	3304		T9	1343		T10	1
auto[1572864:2097151]	329545	1			T4	4235		T7	14		T9	2
auto[2097152:2621439]	361611	1			T2	1		T4	2032		T9	678
auto[2621440:3145727]	291629	1			T4	4215		T9	4294		T10	835
auto[3145728:3670015]	398299	1			T4	9381		T9	9249		T10	618
auto[3670016:4194303]	351808	1			T4	517		T9	1401		T10	69

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1891240

1

T2

1

T4

26112

T7

5

auto[1]

1108147

1

T4

9

T7

14

T9

18934

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2644436

1

T2

1

T4

16042

T7

19

auto[1]

354951

1

T4

10079

T18

2559

T28

1732

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	217589	1			T4	13		T7	5		T9	652
auto[0]	auto[0]	auto[0:524287]	auto[1]	302524	1			T4	777		T18	1		T21	259
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	172298	1			T4	1		T9	1397		T13	225
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	182177	1			T4	769		T18	1247		T28	388
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	117517	1			T4	3		T9	1343		T10	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	138423	1			T4	6		T18	130		T28	256
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	96661	1			T4	9		T7	14		T9	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	196458	1			T4	4171		T18	1725		T28	919
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	159471	1			T2	1		T4	11		T9	678
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	151680	1			T4	1951		T28	515		T21	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	103269	1			T4	6		T9	4294		T10	835
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	144996	1			T4	4195		T18	229		T55	472
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	144692	1			T4	4		T9	9249		T10	618
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	196288	1			T4	3418		T18	920		T28	551
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	112033	1			T4	3		T9	1401		T10	69
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	195128	1			T4	512		T18	258		T28	277
auto[0]	auto[1]	auto[0:524287]	auto[0]	265	1			T4	2		T28	3		T34	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	48645	1			T28	602		T47	256		T33	128
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	402	1			T4	1		T55	2		T31	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	39631	1			T4	769		T55	1706		T47	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	320	1			T4	1		T31	3		T32	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	39555	1			T4	3264		T28	512		T31	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	236	1			T21	4		T55	1		T31	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	33980	1			T21	128		T32	519		T67	130
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	229	1			T4	3		T18	5		T28	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	48263	1			T4	1		T18	2413		T28	384
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	251	1			T4	3		T55	4		T32	6
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	41493	1			T4	1		T55	768		T32	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	268	1			T4	5		T28	2		T47	8
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	55271	1			T4	5890		T47	433		T67	1152
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	236	1			T4	2		T18	2		T28	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	42235	1			T18	129		T28	184		T31	256
auto[1]	auto[0]	auto[0:524287]	auto[0]	238	1			T4	4		T18	1		T21	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	1944	1			T4	43		T18	1		T21	3
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	155	1			T4	1		T18	1		T28	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1547	1			T4	2		T18	3		T28	40
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	176	1			T4	1		T18	2		T31	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1735	1			T4	29		T18	2		T31	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	178	1			T4	3		T18	1		T28	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1618	1			T4	52		T18	5		T28	91
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	178	1			T4	3		T28	3		T21	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1289	1			T4	54		T28	33		T31	6
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	141	1			T55	1		T31	1		T32	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	944	1			T31	3		T32	17		T188	47
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	164	1			T4	1		T28	1		T32	6
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1279	1			T28	38		T32	37		T33	282
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	167	1			T18	2		T28	1		T31	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1479	1			T18	10		T28	1		T31	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	46	1			T28	1		T92	2		T191	4
auto[1]	auto[1]	auto[0:524287]	auto[1]	406	1			T28	9		T92	12		T191	94
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	37	1			T4	1		T38	1		T92	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	448	1			T4	54		T38	28		T92	16
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	38	1			T32	2		T67	1		T53	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	379	1			T32	27		T53	31		T42	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	46	1			T32	2		T67	2		T98	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	368	1			T32	21		T67	2		T98	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	53	1			T4	1		T18	2		T31	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	448	1			T4	8		T18	8		T31	11
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	43	1			T4	1		T32	1		T47	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	492	1			T4	9		T32	11		T47	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	42	1			T4	1		T47	1		T33	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	295	1			T4	62		T47	1		T33	12
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	42	1			T28	1		T32	1		T67	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	488	1			T28	27		T32	14		T92	27

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1523608	1			T2	1		T4	15844		T7	5
auto[0]	auto[0]	auto[1]	1107596	1			T4	5		T7	14		T9	18934
auto[0]	auto[1]	auto[0]	351009	1			T4	9939		T18	2549		T28	1692
auto[0]	auto[1]	auto[1]	271	1			T4	3		T28	2		T31	1
auto[1]	auto[0]	auto[0]	13017	1			T4	192		T18	28		T28	213
auto[1]	auto[0]	auto[1]	215	1			T4	1		T28	1		T21	1
auto[1]	auto[1]	auto[0]	3606	1			T4	137		T18	10		T28	38
auto[1]	auto[1]	auto[1]	65	1			T31	2		T32	4		T98	1