Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13821

1

T4

382

T9

6

T10

12

auto[1]

9223

1

T4

188

T15

10

T31

109

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2123	1			T4	43		T10	12		T17	8
values[1]	2920	1			T4	40		T9	6		T37	14
values[2]	2516	1			T4	27		T89	16		T34	14
values[3]	3107	1			T31	40		T32	63		T45	20
values[4]	2983	1			T4	20		T14	2		T74	4
values[5]	2585	1			T4	99		T31	46		T48	20
values[6]	3783	1			T4	318		T15	10		T31	20
values[7]	3027	1			T4	23		T31	27		T32	51

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2880	1			T4	246		T90	12		T32	32
values[1]	2713	1			T4	43		T89	16		T194	24
values[2]	3118	1			T4	50		T31	60		T32	52
values[3]	3339	1			T4	141		T10	12		T15	10
values[4]	2403	1			T4	47		T9	6		T36	16
values[5]	2807	1			T32	96		T46	6		T67	25
values[6]	3069	1			T4	20		T14	2		T74	4
values[7]	2715	1			T4	23		T17	8		T37	14

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	110	1			T90	12		T39	13		T155	11
auto[0]	values[0]	values[1]	174	1			T4	12		T194	24		T31	11
auto[0]	values[0]	values[2]	126	1			T31	11		T42	15		T43	16
auto[0]	values[0]	values[3]	99	1			T10	12		T32	13		T198	16
auto[0]	values[0]	values[4]	392	1			T4	12		T36	16		T195	10
auto[0]	values[0]	values[5]	85	1			T46	6		T53	24		T218	7
auto[0]	values[0]	values[6]	347	1			T184	13		T39	16		T41	14
auto[0]	values[0]	values[7]	97	1			T17	8		T35	8		T42	10
auto[0]	values[1]	values[0]	199	1			T32	18		T302	22		T325	4
auto[0]	values[1]	values[1]	129	1			T4	11		T43	11		T326	2
auto[0]	values[1]	values[2]	376	1			T38	43		T186	10		T41	14
auto[0]	values[1]	values[3]	216	1			T32	13		T33	11		T99	18
auto[0]	values[1]	values[4]	156	1			T9	6		T42	9		T327	16
auto[0]	values[1]	values[5]	264	1			T39	21		T40	15		T42	13
auto[0]	values[1]	values[6]	167	1			T4	11		T229	14		T237	15
auto[0]	values[1]	values[7]	259	1			T37	14		T32	56		T41	36
auto[0]	values[2]	values[0]	146	1			T33	9		T305	18		T235	2
auto[0]	values[2]	values[1]	84	1			T89	16		T216	6		T324	8
auto[0]	values[2]	values[2]	171	1			T213	20		T23	22		T56	24
auto[0]	values[2]	values[3]	267	1			T31	13		T32	17		T42	6
auto[0]	values[2]	values[4]	112	1			T4	9		T201	14		T298	18
auto[0]	values[2]	values[5]	332	1			T32	43		T67	13		T33	150
auto[0]	values[2]	values[6]	73	1			T273	11		T57	14		T281	6
auto[0]	values[2]	values[7]	186	1			T34	14		T31	14		T38	62
auto[0]	values[3]	values[0]	303	1			T38	25		T186	72		T23	9
auto[0]	values[3]	values[1]	221	1			T32	9		T38	10		T207	10
auto[0]	values[3]	values[2]	256	1			T31	13		T38	62		T186	12
auto[0]	values[3]	values[3]	274	1			T31	13		T49	2		T51	4
auto[0]	values[3]	values[4]	145	1			T53	10		T184	10		T40	24
auto[0]	values[3]	values[5]	229	1			T53	10		T198	23		T328	10
auto[0]	values[3]	values[6]	408	1			T32	35		T38	19		T99	11
auto[0]	values[3]	values[7]	147	1			T99	19		T23	17		T237	18
auto[0]	values[4]	values[0]	192	1			T106	16		T236	14		T254	59
auto[0]	values[4]	values[1]	233	1			T186	13		T42	14		T318	10
auto[0]	values[4]	values[2]	331	1			T4	16		T33	13		T214	20
auto[0]	values[4]	values[3]	201	1			T32	3		T204	10		T329	10
auto[0]	values[4]	values[4]	166	1			T38	15		T41	8		T43	13
auto[0]	values[4]	values[5]	228	1			T32	15		T39	7		T330	2
auto[0]	values[4]	values[6]	174	1			T14	2		T74	4		T207	13
auto[0]	values[4]	values[7]	228	1			T31	25		T241	17		T331	4
auto[0]	values[5]	values[0]	154	1			T4	11		T48	20		T33	33
auto[0]	values[5]	values[1]	258	1			T67	31		T183	8		T220	10
auto[0]	values[5]	values[2]	236	1			T31	9		T53	39		T33	79
auto[0]	values[5]	values[3]	170	1			T332	12		T243	28		T41	10
auto[0]	values[5]	values[4]	134	1			T53	9		T155	11		T254	10
auto[0]	values[5]	values[5]	87	1			T186	7		T228	11		T333	6
auto[0]	values[5]	values[6]	216	1			T31	15		T53	13		T99	12
auto[0]	values[5]	values[7]	227	1			T184	13		T186	8		T233	2
auto[0]	values[6]	values[0]	394	1			T4	139		T198	15		T185	9
auto[0]	values[6]	values[1]	260	1			T33	76		T185	11		T334	6
auto[0]	values[6]	values[2]	156	1			T4	25		T32	14		T250	9
auto[0]	values[6]	values[3]	365	1			T4	127		T31	13		T33	172
auto[0]	values[6]	values[4]	115	1			T185	7		T206	13		T91	8
auto[0]	values[6]	values[5]	392	1			T53	12		T196	52		T40	12
auto[0]	values[6]	values[6]	269	1			T33	10		T38	10		T335	22
auto[0]	values[6]	values[7]	333	1			T53	7		T40	101		T198	33
auto[0]	values[7]	values[0]	226	1			T219	10		T38	8		T42	10
auto[0]	values[7]	values[1]	270	1			T31	9		T200	2		T23	7
auto[0]	values[7]	values[2]	222	1			T64	10		T228	53		T197	15
auto[0]	values[7]	values[3]	295	1			T40	12		T217	10		T43	13
auto[0]	values[7]	values[4]	238	1			T32	15		T207	13		T319	16
auto[0]	values[7]	values[5]	128	1			T32	17		T215	10		T336	8
auto[0]	values[7]	values[6]	174	1			T246	10		T43	11		T240	26
auto[0]	values[7]	values[7]	199	1			T4	9		T33	23		T155	15
auto[1]	values[0]	values[0]	49	1			T39	7		T155	13		T162	9
auto[1]	values[0]	values[1]	115	1			T4	11		T31	9		T205	6
auto[1]	values[0]	values[2]	90	1			T31	9		T42	7		T43	4
auto[1]	values[0]	values[3]	55	1			T32	19		T198	4		T230	8
auto[1]	values[0]	values[4]	146	1			T4	8		T99	23		T186	14
auto[1]	values[0]	values[5]	51	1			T53	16		T218	13		T237	5
auto[1]	values[0]	values[6]	103	1			T184	7		T39	4		T41	10
auto[1]	values[0]	values[7]	84	1			T42	10		T197	12		T266	9
auto[1]	values[1]	values[0]	120	1			T32	14		T238	10		T269	12
auto[1]	values[1]	values[1]	54	1			T4	9		T43	9		T266	11
auto[1]	values[1]	values[2]	190	1			T38	6		T186	10		T41	6
auto[1]	values[1]	values[3]	220	1			T32	34		T33	9		T99	5
auto[1]	values[1]	values[4]	135	1			T42	13		T212	6		T263	4
auto[1]	values[1]	values[5]	222	1			T39	8		T40	50		T42	7
auto[1]	values[1]	values[6]	92	1			T4	9		T270	4		T237	8
auto[1]	values[1]	values[7]	121	1			T32	24		T41	7		T44	22
auto[1]	values[2]	values[0]	199	1			T33	11		T314	24		T248	13
auto[1]	values[2]	values[1]	43	1			T197	6		T257	15		T256	10
auto[1]	values[2]	values[2]	82	1			T23	21		T56	6		T161	9
auto[1]	values[2]	values[3]	320	1			T31	9		T32	47		T42	20
auto[1]	values[2]	values[4]	134	1			T4	18		T201	19		T222	8
auto[1]	values[2]	values[5]	204	1			T32	6		T67	12		T33	11
auto[1]	values[2]	values[6]	56	1			T337	2		T338	10		T273	13
auto[1]	values[2]	values[7]	107	1			T31	10		T38	8		T186	8
auto[1]	values[3]	values[0]	96	1			T38	8		T186	13		T23	11
auto[1]	values[3]	values[1]	184	1			T32	11		T38	10		T207	10
auto[1]	values[3]	values[2]	135	1			T31	7		T38	51		T186	8
auto[1]	values[3]	values[3]	220	1			T31	7		T45	20		T33	10
auto[1]	values[3]	values[4]	107	1			T53	43		T184	10		T40	4
auto[1]	values[3]	values[5]	91	1			T53	10		T198	8		T339	10
auto[1]	values[3]	values[6]	157	1			T32	8		T38	8		T99	9
auto[1]	values[3]	values[7]	134	1			T99	6		T23	3		T237	2
auto[1]	values[4]	values[0]	65	1			T254	5		T283	7		T248	10
auto[1]	values[4]	values[1]	124	1			T186	59		T42	6		T91	14
auto[1]	values[4]	values[2]	315	1			T4	4		T33	47		T228	4
auto[1]	values[4]	values[3]	160	1			T32	53		T91	11		T269	7
auto[1]	values[4]	values[4]	87	1			T38	8		T41	23		T43	7
auto[1]	values[4]	values[5]	159	1			T32	5		T39	21		T304	22
auto[1]	values[4]	values[6]	162	1			T207	34		T56	10		T155	9
auto[1]	values[4]	values[7]	158	1			T31	11		T241	4		T230	4
auto[1]	values[5]	values[0]	270	1			T4	88		T33	11		T222	14
auto[1]	values[5]	values[1]	118	1			T67	9		T40	7		T340	6
auto[1]	values[5]	values[2]	105	1			T31	11		T53	15		T33	3
auto[1]	values[5]	values[3]	142	1			T41	10		T201	4		T91	10
auto[1]	values[5]	values[4]	112	1			T53	11		T341	10		T155	10
auto[1]	values[5]	values[5]	65	1			T186	13		T228	9		T261	6
auto[1]	values[5]	values[6]	144	1			T31	11		T53	7		T99	8
auto[1]	values[5]	values[7]	147	1			T184	7		T186	12		T201	21
auto[1]	values[6]	values[0]	216	1			T4	8		T198	5		T185	13
auto[1]	values[6]	values[1]	184	1			T33	75		T208	18		T185	10
auto[1]	values[6]	values[2]	158	1			T4	5		T32	38		T250	11
auto[1]	values[6]	values[3]	93	1			T4	14		T15	10		T31	7
auto[1]	values[6]	values[4]	114	1			T66	24		T185	13		T206	8
auto[1]	values[6]	values[5]	171	1			T53	9		T40	8		T185	6
auto[1]	values[6]	values[6]	426	1			T33	10		T38	10		T226	10
auto[1]	values[6]	values[7]	137	1			T53	13		T40	3		T198	7
auto[1]	values[7]	values[0]	141	1			T38	12		T42	10		T201	25
auto[1]	values[7]	values[1]	262	1			T31	18		T23	25		T226	42
auto[1]	values[7]	values[2]	169	1			T228	9		T197	11		T91	8
auto[1]	values[7]	values[3]	242	1			T40	29		T43	7		T185	54
auto[1]	values[7]	values[4]	110	1			T32	9		T207	40		T226	10
auto[1]	values[7]	values[5]	99	1			T32	10		T242	2		T212	15
auto[1]	values[7]	values[6]	101	1			T43	9		T56	10		T271	18
auto[1]	values[7]	values[7]	151	1			T4	14		T33	7		T155	6