Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	284	1			T4	4		T10	6		T194	6
auto[ReadAddrCrossIntoMailbox]	225	1			T4	3		T194	2		T31	1
auto[ReadAddrCrossOutOfMailbox]	214	1			T4	1		T194	2		T31	3
auto[ReadAddrCrossAllMailbox]	148	1			T4	1		T194	6		T31	2
auto[ReadAddrOutsideMailbox]	2756	1			T4	44		T14	2		T15	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1783

1

T4

30

T10

3

T14

1

auto[1]

1844

1

T4

23

T10

3

T14

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	573	1			T4	8		T195	2		T31	9
read_ops[0x0b]	577	1			T4	11		T17	2		T89	6
read_ops[0x3b]	626	1			T4	8		T17	2		T74	2
read_ops[0x6b]	581	1			T4	11		T10	4		T90	2
read_ops[0xbb]	630	1			T4	4		T15	4		T17	2
read_ops[0xeb]	640	1			T4	11		T10	2		T14	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T46	1		T186	1		T243	4
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T31	3		T46	1		T67	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	12	1			T221	1		T222	2		T56	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T67	1		T221	1		T42	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T53	1		T40	1		T42	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T198	1		T241	1		T342	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T197	1		T222	1		T343	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T38	1		T197	1		T241	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	190	1			T4	4		T195	1		T31	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	231	1			T4	4		T195	1		T31	5
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T4	1		T46	1		T67	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T32	1		T46	1		T33	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T33	2		T40	1		T343	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T32	1		T42	1		T201	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T31	1		T67	1		T53	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T185	1		T344	1		T241	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	7	1			T23	1		T56	1		T155	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T53	1		T185	1		T226	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	209	1			T4	7		T17	1		T89	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	222	1			T4	3		T17	1		T89	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	19	1			T38	1		T41	1		T42	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T40	1		T324	1		T43	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T53	1		T99	1		T43	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T31	1		T39	1		T198	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T31	1		T41	1		T324	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T32	2		T99	1		T42	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T31	1		T32	1		T33	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T345	1		T247	1		T91	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	244	1			T4	7		T17	1		T74	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	232	1			T4	1		T17	1		T74	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	19	1			T10	2		T194	1		T216	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T4	1		T10	2		T194	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T4	1		T194	1		T53	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T4	1		T194	1		T43	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T194	1		T33	1		T186	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T194	1		T33	1		T197	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T185	1		T226	1		T241	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	9	1			T32	1		T201	1		T237	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	233	1			T4	2		T90	1		T194	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	218	1			T4	6		T90	1		T194	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T194	1		T31	2		T41	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T194	1		T31	1		T32	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T184	1		T33	2		T185	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T4	1		T38	1		T39	3
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T31	1		T53	1		T38	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	9	1			T345	1		T241	1		T254	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T38	1		T345	1		T266	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T31	1		T38	2		T345	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	251	1			T4	2		T15	2		T17	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	244	1			T4	1		T15	2		T17	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T4	1		T10	1		T194	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T4	1		T10	1		T194	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T32	1		T324	1		T201	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	11	1			T324	1		T344	1		T222	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T4	1		T324	1		T201	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T99	1		T40	1		T186	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T4	1		T194	3		T197	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T194	3		T67	1		T186	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	220	1			T4	3		T14	1		T37	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	262	1			T4	4		T14	1		T37	1