Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2645846	1			T1	1		T2	1		T3	1
all_pins[1]	2645846	1			T1	1		T2	1		T3	1
all_pins[2]	2645846	1			T1	1		T2	1		T3	1
all_pins[3]	2645846	1			T1	1		T2	1		T3	1
all_pins[4]	2645846	1			T1	1		T2	1		T3	1
all_pins[5]	2645846	1			T1	1		T2	1		T3	1
all_pins[6]	2645846	1			T1	1		T2	1		T3	1
all_pins[7]	2645846	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21055485	1			T1	8		T2	8		T3	8
values[0x1]	111283	1			T18	1806		T47	20		T68	56
transitions[0x0=>0x1]	109697	1			T18	1799		T47	9		T68	38
transitions[0x1=>0x0]	109706	1			T18	1799		T47	10		T68	38

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2645048	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	798	1			T47	2		T68	8		T67	3
all_pins[0]	transitions[0x0=>0x1]	502	1			T47	1		T68	6		T67	3
all_pins[0]	transitions[0x1=>0x0]	213	1			T18	2		T47	3		T68	4
all_pins[1]	values[0x0]	2645337	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	509	1			T18	2		T47	4		T68	6
all_pins[1]	transitions[0x0=>0x1]	401	1			T18	2		T68	2		T67	29
all_pins[1]	transitions[0x1=>0x0]	154	1			T18	4		T47	2		T68	6
all_pins[2]	values[0x0]	2645584	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	262	1			T18	4		T47	6		T68	10
all_pins[2]	transitions[0x0=>0x1]	210	1			T18	1		T47	3		T68	6
all_pins[2]	transitions[0x1=>0x0]	130	1			T18	4		T68	1		T100	6
all_pins[3]	values[0x0]	2645664	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	182	1			T18	7		T47	3		T68	5
all_pins[3]	transitions[0x0=>0x1]	142	1			T18	5		T47	2		T68	2
all_pins[3]	transitions[0x1=>0x0]	124	1			T68	4		T67	2		T100	1
all_pins[4]	values[0x0]	2645682	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	164	1			T18	2		T47	1		T68	7
all_pins[4]	transitions[0x0=>0x1]	125	1			T18	2		T47	1		T68	6
all_pins[4]	transitions[0x1=>0x0]	1375	1			T18	1		T68	5		T100	1
all_pins[5]	values[0x0]	2644432	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	1414	1			T18	1		T68	6		T67	2
all_pins[5]	transitions[0x0=>0x1]	467	1			T18	1		T68	5		T67	1
all_pins[5]	transitions[0x1=>0x0]	106803	1			T18	1788		T47	1		T68	6
all_pins[6]	values[0x0]	2538096	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	107750	1			T18	1788		T47	1		T68	7
all_pins[6]	transitions[0x0=>0x1]	107702	1			T18	1786		T47	1		T68	6
all_pins[6]	transitions[0x1=>0x0]	156	1			T47	3		T68	6		T67	1
all_pins[7]	values[0x0]	2645642	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	204	1			T18	2		T47	3		T68	7
all_pins[7]	transitions[0x0=>0x1]	148	1			T18	2		T47	1		T68	5
all_pins[7]	transitions[0x1=>0x0]	751	1			T47	1		T68	6		T67	2