Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3154	1			T4	288		T195	10		T32	47
values[1]	2743	1			T4	46		T14	2		T89	16
values[2]	2598	1			T4	97		T17	8		T31	46
values[3]	3019	1			T36	16		T35	8		T31	44
values[4]	3209	1			T4	119		T9	6		T74	4
values[5]	2643	1			T15	10		T31	27		T32	161
values[6]	3076	1			T10	12		T90	12		T194	24
values[7]	2602	1			T4	20		T37	14		T31	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2542	1			T36	16		T31	24		T32	20
values[1]	3008	1			T4	181		T74	4		T195	10
values[2]	2852	1			T4	20		T15	10		T89	16
values[3]	2950	1			T4	174		T37	14		T31	20
values[4]	3116	1			T4	122		T10	12		T194	24
values[5]	2925	1			T4	20		T17	8		T31	78
values[6]	2739	1			T14	2		T32	129		T67	25
values[7]	2912	1			T4	53		T9	6		T90	12

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22679

1

T4

567

T9

6

T10

12

auto[1]

365

1

T4

3

T31

4

T32

7

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[4]]	[values[3]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	549	1			T53	20		T39	19		T196	52
auto[0]	values[0]	values[1]	426	1			T4	140		T195	10		T53	20
auto[0]	values[0]	values[2]	374	1			T33	101		T43	20		T197	20
auto[0]	values[0]	values[3]	711	1			T4	146		T33	177		T198	20
auto[0]	values[0]	values[4]	157	1			T32	46		T155	20		T199	20
auto[0]	values[0]	values[5]	276	1			T200	2		T186	85		T201	21
auto[0]	values[0]	values[6]	231	1			T67	25		T38	69		T186	20
auto[0]	values[0]	values[7]	385	1			T67	20		T40	19		T23	22
auto[0]	values[1]	values[0]	337	1			T38	61		T186	72		T202	14
auto[0]	values[1]	values[1]	244	1			T53	20		T33	60		T38	18
auto[0]	values[1]	values[2]	496	1			T89	16		T32	40		T46	6
auto[0]	values[1]	values[3]	265	1			T51	4		T203	2		T204	10
auto[0]	values[1]	values[4]	435	1			T4	23		T205	6		T40	104
auto[0]	values[1]	values[5]	244	1			T31	20		T42	24		T206	19
auto[0]	values[1]	values[6]	255	1			T14	2		T207	20		T208	16
auto[0]	values[1]	values[7]	415	1			T4	23		T184	20		T99	20
auto[0]	values[2]	values[0]	217	1			T32	20		T209	6		T99	25
auto[0]	values[2]	values[1]	432	1			T4	20		T99	22		T43	20
auto[0]	values[2]	values[2]	114	1			T210	6		T211	4		T212	22
auto[0]	values[2]	values[3]	431	1			T4	27		T49	2		T43	40
auto[0]	values[2]	values[4]	337	1			T31	25		T53	34		T213	20
auto[0]	values[2]	values[5]	223	1			T4	20		T17	8		T214	20
auto[0]	values[2]	values[6]	327	1			T53	20		T43	20		T66	24
auto[0]	values[2]	values[7]	473	1			T4	30		T31	20		T41	42
auto[0]	values[3]	values[0]	304	1			T36	16		T31	23		T39	19
auto[0]	values[3]	values[1]	368	1			T48	20		T198	92		T201	34
auto[0]	values[3]	values[2]	344	1			T35	8		T33	44		T43	20
auto[0]	values[3]	values[3]	343	1			T32	30		T53	53		T99	20
auto[0]	values[3]	values[4]	389	1			T31	20		T32	60		T215	10
auto[0]	values[3]	values[5]	587	1			T67	20		T216	6		T201	30
auto[0]	values[3]	values[6]	369	1			T217	10		T23	22		T218	20
auto[0]	values[3]	values[7]	267	1			T32	42		T33	20		T43	17
auto[0]	values[4]	values[0]	201	1			T53	21		T219	10		T40	21
auto[0]	values[4]	values[1]	193	1			T74	4		T220	10		T221	8
auto[0]	values[4]	values[2]	674	1			T4	20		T34	14		T32	62
auto[0]	values[4]	values[3]	246	1			T40	20		T222	20		T223	73
auto[0]	values[4]	values[4]	544	1			T4	98		T99	25		T40	41
auto[0]	values[4]	values[5]	241	1			T32	27		T56	20		T224	19
auto[0]	values[4]	values[6]	507	1			T184	20		T33	83		T38	49
auto[0]	values[4]	values[7]	551	1			T9	6		T33	30		T38	20
auto[0]	values[5]	values[0]	262	1			T38	42		T225	8		T226	20
auto[0]	values[5]	values[1]	511	1			T31	27		T32	32		T227	8
auto[0]	values[5]	values[2]	99	1			T15	10		T228	32		T159	10
auto[0]	values[5]	values[3]	193	1			T38	25		T229	14		T230	20
auto[0]	values[5]	values[4]	461	1			T45	20		T99	20		T186	20
auto[0]	values[5]	values[5]	500	1			T38	32		T198	50		T185	46
auto[0]	values[5]	values[6]	467	1			T32	128		T33	69		T186	20
auto[0]	values[5]	values[7]	102	1			T186	19		T185	20		T231	8
auto[0]	values[6]	values[0]	363	1			T201	30		T185	21		T232	20
auto[0]	values[6]	values[1]	476	1			T39	29		T233	2		T228	62
auto[0]	values[6]	values[2]	326	1			T31	20		T234	10		T155	21
auto[0]	values[6]	values[3]	425	1			T235	2		T236	14		T237	20
auto[0]	values[6]	values[4]	325	1			T10	12		T194	24		T238	10
auto[0]	values[6]	values[5]	504	1			T31	56		T239	4		T240	26
auto[0]	values[6]	values[6]	265	1			T43	20		T197	102		T241	30
auto[0]	values[6]	values[7]	353	1			T90	12		T53	20		T185	65
auto[0]	values[7]	values[0]	267	1			T53	20		T242	2		T185	28
auto[0]	values[7]	values[1]	320	1			T4	20		T31	20		T243	28
auto[0]	values[7]	values[2]	383	1			T32	52		T33	20		T186	20
auto[0]	values[7]	values[3]	293	1			T37	14		T31	20		T91	20
auto[0]	values[7]	values[4]	418	1			T33	161		T244	10		T245	10
auto[0]	values[7]	values[5]	297	1			T184	19		T33	65		T43	39
auto[0]	values[7]	values[6]	265	1			T39	28		T246	10		T42	18
auto[0]	values[7]	values[7]	322	1			T183	8		T185	23		T247	16
auto[1]	values[0]	values[0]	9	1			T39	1		T248	2		T249	1
auto[1]	values[0]	values[1]	4	1			T4	1		T250	1		T162	2
auto[1]	values[0]	values[2]	4	1			T33	1		T251	2		T252	1
auto[1]	values[0]	values[3]	12	1			T4	1		T201	1		T161	1
auto[1]	values[0]	values[4]	3	1			T32	1		T253	2		-	-
auto[1]	values[0]	values[5]	1	1			T201	1		-	-		-	-
auto[1]	values[0]	values[6]	3	1			T38	1		T248	2		-	-
auto[1]	values[0]	values[7]	9	1			T40	1		T162	2		T199	1
auto[1]	values[1]	values[0]	7	1			T254	3		T255	4		-	-
auto[1]	values[1]	values[1]	3	1			T38	2		T256	1		-	-
auto[1]	values[1]	values[2]	10	1			T40	1		T56	1		T257	1
auto[1]	values[1]	values[3]	3	1			T254	3		-	-		-	-
auto[1]	values[1]	values[4]	7	1			T258	2		T259	4		T260	1
auto[1]	values[1]	values[5]	11	1			T31	2		T42	2		T206	2
auto[1]	values[1]	values[6]	8	1			T208	2		T261	2		T257	2
auto[1]	values[1]	values[7]	3	1			T201	2		T262	1		-	-
auto[1]	values[2]	values[0]	4	1			T99	2		T257	1		T253	1
auto[1]	values[2]	values[1]	3	1			T99	1		T201	1		T263	1
auto[1]	values[2]	values[2]	6	1			T165	1		T264	5		-	-
auto[1]	values[2]	values[3]	11	1			T265	2		T56	2		T266	1
auto[1]	values[2]	values[4]	5	1			T31	1		T42	1		T218	1
auto[1]	values[2]	values[5]	2	1			T267	2		-	-		-	-
auto[1]	values[2]	values[6]	5	1			T185	1		T254	2		T161	2
auto[1]	values[2]	values[7]	8	1			T41	1		T224	3		T268	2
auto[1]	values[3]	values[0]	4	1			T31	1		T39	1		T269	2
auto[1]	values[3]	values[1]	7	1			T201	1		T270	2		T224	2
auto[1]	values[3]	values[2]	1	1			T23	1		-	-		-	-
auto[1]	values[3]	values[3]	6	1			T32	2		T23	1		T271	1
auto[1]	values[3]	values[4]	11	1			T198	1		T272	6		T57	1
auto[1]	values[3]	values[5]	10	1			T201	1		T197	1		T237	2
auto[1]	values[3]	values[6]	5	1			T23	1		T273	3		T274	1
auto[1]	values[3]	values[7]	4	1			T32	1		T43	3		-	-
auto[1]	values[4]	values[0]	2	1			T275	2		-	-		-	-
auto[1]	values[4]	values[1]	3	1			T276	1		T277	1		T278	1
auto[1]	values[4]	values[2]	8	1			T32	2		T33	1		T248	3
auto[1]	values[4]	values[4]	13	1			T4	1		T198	1		T56	2
auto[1]	values[4]	values[5]	4	1			T224	3		T253	1		-	-
auto[1]	values[4]	values[6]	13	1			T33	3		T226	2		T258	1
auto[1]	values[4]	values[7]	9	1			T44	4		T249	3		T274	1
auto[1]	values[5]	values[0]	5	1			T38	1		T279	2		T280	2
auto[1]	values[5]	values[1]	5	1			T56	3		T267	1		T281	1
auto[1]	values[5]	values[2]	4	1			T228	1		T159	2		T260	1
auto[1]	values[5]	values[3]	5	1			T38	2		T269	2		T282	1
auto[1]	values[5]	values[4]	4	1			T162	2		T283	2		-	-
auto[1]	values[5]	values[5]	14	1			T38	1		T198	1		T185	3
auto[1]	values[5]	values[6]	10	1			T32	1		T41	1		T230	2
auto[1]	values[5]	values[7]	1	1			T186	1		-	-		-	-
auto[1]	values[6]	values[0]	4	1			T237	2		T277	1		T284	1
auto[1]	values[6]	values[1]	9	1			T273	2		T224	3		T57	1
auto[1]	values[6]	values[2]	6	1			T155	3		T254	1		T282	1
auto[1]	values[6]	values[3]	4	1			T267	3		T268	1		-	-
auto[1]	values[6]	values[4]	3	1			T198	1		T57	2		-	-
auto[1]	values[6]	values[5]	6	1			T162	1		T256	1		T255	4
auto[1]	values[6]	values[6]	2	1			T224	1		T256	1		-	-
auto[1]	values[6]	values[7]	5	1			T285	1		T281	3		T286	1
auto[1]	values[7]	values[0]	7	1			T185	1		T287	1		T288	2
auto[1]	values[7]	values[1]	4	1			T257	1		T279	3		-	-
auto[1]	values[7]	values[2]	3	1			T257	2		T289	1		-	-
auto[1]	values[7]	values[3]	2	1			T281	2		-	-		-	-
auto[1]	values[7]	values[4]	4	1			T273	2		T267	1		T274	1
auto[1]	values[7]	values[5]	5	1			T184	1		T43	1		T91	1
auto[1]	values[7]	values[6]	7	1			T42	4		T249	1		T279	2
auto[1]	values[7]	values[7]	5	1			T269	2		T271	2		T275	1