Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1850

1

T1

4

T3

23

T6

1

auto[1]

1791

1

T1

1

T3

10

T16

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2035

1

T6

1

T18

8

T20

8

auto[1]

1606

1

T1

5

T3

33

T16

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2878

1

T1

5

T3

33

T6

1

auto[1]

763

1

T18

3

T20

2

T21

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	713	1			T1	1		T3	7		T6	1
valid[1]	746	1			T3	7		T18	2		T19	7
valid[2]	759	1			T1	1		T3	6		T16	3
valid[3]	685	1			T1	1		T3	5		T16	1
valid[4]	738	1			T1	2		T3	8		T18	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	127	1			T6	1		T30	2		T29	1
auto[0]	auto[0]	valid[0]	auto[1]	171	1			T1	1		T3	5		T16	1
auto[0]	auto[0]	valid[1]	auto[0]	142	1			T18	2		T20	1		T29	1
auto[0]	auto[0]	valid[1]	auto[1]	189	1			T3	7		T19	6		T104	1
auto[0]	auto[0]	valid[2]	auto[0]	128	1			T20	1		T29	2		T55	1
auto[0]	auto[0]	valid[2]	auto[1]	168	1			T1	1		T3	2		T16	1
auto[0]	auto[0]	valid[3]	auto[0]	124	1			T20	1		T30	1		T29	2
auto[0]	auto[0]	valid[3]	auto[1]	131	1			T1	1		T3	4		T16	1
auto[0]	auto[0]	valid[4]	auto[0]	150	1			T30	1		T29	1		T55	1
auto[0]	auto[0]	valid[4]	auto[1]	137	1			T1	1		T3	5		T19	1
auto[0]	auto[1]	valid[0]	auto[0]	111	1			T20	1		T30	1		T29	3
auto[0]	auto[1]	valid[0]	auto[1]	156	1			T3	2		T19	4		T105	1
auto[0]	auto[1]	valid[1]	auto[0]	123	1			T20	1		T30	2		T29	2
auto[0]	auto[1]	valid[1]	auto[1]	147	1			T19	1		T104	2		T364	1
auto[0]	auto[1]	valid[2]	auto[0]	124	1			T18	2		T30	1		T29	1
auto[0]	auto[1]	valid[2]	auto[1]	184	1			T3	4		T16	2		T19	1
auto[0]	auto[1]	valid[3]	auto[0]	116	1			T30	1		T67	2		T53	1
auto[0]	auto[1]	valid[3]	auto[1]	162	1			T3	1		T19	6		T104	1
auto[0]	auto[1]	valid[4]	auto[0]	127	1			T18	1		T20	1		T21	1
auto[0]	auto[1]	valid[4]	auto[1]	161	1			T1	1		T3	3		T19	6
auto[1]	auto[0]	valid[0]	auto[0]	82	1			T30	1		T29	1		T47	1
auto[1]	auto[0]	valid[1]	auto[0]	74	1			T29	1		T47	1		T50	1
auto[1]	auto[0]	valid[2]	auto[0]	70	1			T20	1		T47	3		T50	1
auto[1]	auto[0]	valid[3]	auto[0]	71	1			T29	1		T55	1		T67	1
auto[1]	auto[0]	valid[4]	auto[0]	86	1			T30	1		T53	2		T100	1
auto[1]	auto[1]	valid[0]	auto[0]	66	1			T18	1		T29	1		T67	1
auto[1]	auto[1]	valid[1]	auto[0]	71	1			T55	1		T53	1		T100	1
auto[1]	auto[1]	valid[2]	auto[0]	85	1			T20	1		T21	1		T29	1
auto[1]	auto[1]	valid[3]	auto[0]	81	1			T18	1		T29	1		T47	2
auto[1]	auto[1]	valid[4]	auto[0]	77	1			T18	1		T30	3		T29	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal