Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51044

1

T5

7

T6

7

T8

7

auto[1]

16947

1

T1

5

T3

409

T16

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49476

1

T1

5

T3

409

T5

4

auto[1]

18515

1

T5

3

T6

3

T8

3

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35182	1			T1	5		T3	202		T5	6
others[1]	5673	1			T3	42		T18	25		T19	25
others[2]	5757	1			T3	38		T18	28		T19	26
others[3]	6471	1			T3	37		T18	32		T19	34
interest[1]	3725	1			T3	21		T6	2		T18	19
interest[4]	22998	1			T1	5		T3	130		T5	4
interest[64]	11183	1			T3	69		T5	1		T6	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16788	1			T5	4		T6	2		T8	2
auto[0]	auto[0]	others[1]	2759	1			T18	18		T20	11		T21	5
auto[0]	auto[0]	others[2]	2764	1			T18	20		T20	12		T21	1
auto[0]	auto[0]	others[3]	3136	1			T18	22		T20	17		T30	13
auto[0]	auto[0]	interest[1]	1787	1			T6	2		T18	12		T20	8
auto[0]	auto[0]	interest[4]	11026	1			T5	2		T6	2		T8	1
auto[0]	auto[0]	interest[64]	5295	1			T8	2		T18	37		T20	21
auto[0]	auto[1]	others[0]	8802	1			T1	5		T3	202		T16	5
auto[0]	auto[1]	others[1]	1424	1			T3	42		T19	25		T97	2
auto[0]	auto[1]	others[2]	1393	1			T3	38		T19	26		T97	1
auto[0]	auto[1]	others[3]	1584	1			T3	37		T19	34		T97	3
auto[0]	auto[1]	interest[1]	914	1			T3	21		T19	17		T97	1
auto[0]	auto[1]	interest[4]	5754	1			T1	5		T3	130		T16	5
auto[0]	auto[1]	interest[64]	2830	1			T3	69		T19	67		T97	6
auto[1]	auto[0]	others[0]	9592	1			T5	2		T6	1		T8	3
auto[1]	auto[0]	others[1]	1490	1			T18	7		T20	5		T21	2
auto[1]	auto[0]	others[2]	1600	1			T18	8		T20	8		T21	2
auto[1]	auto[0]	others[3]	1751	1			T18	10		T20	7		T21	1
auto[1]	auto[0]	interest[1]	1024	1			T18	7		T20	5		T21	1
auto[1]	auto[0]	interest[4]	6218	1			T5	2		T6	1		T8	1
auto[1]	auto[0]	interest[64]	3058	1			T5	1		T6	2		T18	13

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal