Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	778	1			T18	11		T47	7		T68	21
all_values[1]	778	1			T18	11		T47	7		T68	21
all_values[2]	778	1			T18	11		T47	7		T68	21
all_values[3]	778	1			T18	11		T47	7		T68	21
all_values[4]	778	1			T18	11		T47	7		T68	21
all_values[5]	778	1			T18	11		T47	7		T68	21
all_values[6]	778	1			T18	11		T47	7		T68	21
all_values[7]	778	1			T18	11		T47	7		T68	21

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3279

1

T18

44

T47

28

T68

80

auto[1]

2945

1

T18

44

T47

28

T68

88

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2558

1

T18

41

T47

17

T68

54

auto[1]

3666

1

T18

47

T47

39

T68

114

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3617

1

T18

56

T47

34

T68

90

auto[1]

2607

1

T18

32

T47

22

T68

78

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	146	1			T18	1		T47	2		T68	2
all_values[0]	auto[0]	auto[0]	auto[1]	72	1			T18	2		T47	1		T68	2
all_values[0]	auto[0]	auto[1]	auto[0]	148	1			T18	3		T68	3		T67	2
all_values[0]	auto[0]	auto[1]	auto[1]	83	1			T68	4		T67	1		T100	1
all_values[0]	auto[1]	auto[0]	auto[1]	166	1			T18	5		T47	2		T68	4
all_values[0]	auto[1]	auto[1]	auto[1]	163	1			T47	2		T68	6		T67	4
all_values[1]	auto[0]	auto[0]	auto[0]	153	1			T18	1		T47	1		T68	4
all_values[1]	auto[0]	auto[0]	auto[1]	86	1			T18	1		T68	4		T67	1
all_values[1]	auto[0]	auto[1]	auto[0]	137	1			T18	5		T47	1		T68	1
all_values[1]	auto[0]	auto[1]	auto[1]	75	1			T18	1		T47	2		T68	2
all_values[1]	auto[1]	auto[0]	auto[1]	170	1			T18	1		T47	1		T68	5
all_values[1]	auto[1]	auto[1]	auto[1]	157	1			T18	2		T47	2		T68	5
all_values[2]	auto[0]	auto[0]	auto[0]	147	1			T18	3		T68	4		T100	3
all_values[2]	auto[0]	auto[0]	auto[1]	68	1			T18	2		T68	2		T67	1
all_values[2]	auto[0]	auto[1]	auto[0]	160	1			T18	1		T68	1		T67	1
all_values[2]	auto[0]	auto[1]	auto[1]	77	1			T18	1		T47	4		T68	1
all_values[2]	auto[1]	auto[0]	auto[1]	169	1			T18	2		T68	4		T67	1
all_values[2]	auto[1]	auto[1]	auto[1]	157	1			T18	2		T47	3		T68	9
all_values[3]	auto[0]	auto[0]	auto[0]	167	1			T18	3		T68	1		T67	5
all_values[3]	auto[0]	auto[0]	auto[1]	79	1			T47	1		T68	2		T100	1
all_values[3]	auto[0]	auto[1]	auto[0]	147	1			T18	1		T47	2		T68	6
all_values[3]	auto[0]	auto[1]	auto[1]	70	1			T18	3		T47	2		T68	1
all_values[3]	auto[1]	auto[0]	auto[1]	183	1			T18	1		T68	7		T67	2
all_values[3]	auto[1]	auto[1]	auto[1]	132	1			T18	3		T47	2		T68	4
all_values[4]	auto[0]	auto[0]	auto[0]	177	1			T18	2		T47	2		T68	5
all_values[4]	auto[0]	auto[0]	auto[1]	74	1			T47	2		T68	5		T67	1
all_values[4]	auto[0]	auto[1]	auto[0]	141	1			T18	3		T68	1		T67	1
all_values[4]	auto[0]	auto[1]	auto[1]	63	1			T18	1		T68	2		T67	1
all_values[4]	auto[1]	auto[0]	auto[1]	172	1			T18	3		T47	2		T68	4
all_values[4]	auto[1]	auto[1]	auto[1]	151	1			T18	2		T47	1		T68	4
all_values[5]	auto[0]	auto[0]	auto[0]	248	1			T18	5		T47	4		T68	4
all_values[5]	auto[0]	auto[1]	auto[0]	202	1			T18	2		T47	1		T68	8
all_values[5]	auto[1]	auto[0]	auto[1]	160	1			T18	3		T47	2		T68	3
all_values[5]	auto[1]	auto[1]	auto[1]	168	1			T18	1		T68	6		T67	2
all_values[6]	auto[0]	auto[0]	auto[0]	164	1			T47	4		T68	2		T100	2
all_values[6]	auto[0]	auto[0]	auto[1]	80	1			T47	1		T68	4		T67	1
all_values[6]	auto[0]	auto[1]	auto[0]	140	1			T18	4		T68	6		T67	3
all_values[6]	auto[0]	auto[1]	auto[1]	65	1			T18	3		T68	2		T67	3
all_values[6]	auto[1]	auto[0]	auto[1]	172	1			T68	2		T67	2		T100	3
all_values[6]	auto[1]	auto[1]	auto[1]	157	1			T18	4		T47	2		T68	5
all_values[7]	auto[0]	auto[0]	auto[0]	157	1			T18	7		T68	3		T67	3
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T47	2		T68	3		T67	2
all_values[7]	auto[0]	auto[1]	auto[0]	124	1			T68	3		T67	2		T100	4
all_values[7]	auto[0]	auto[1]	auto[1]	90	1			T18	1		T47	2		T68	2
all_values[7]	auto[1]	auto[0]	auto[1]	192	1			T18	2		T47	1		T68	4
all_values[7]	auto[1]	auto[1]	auto[1]	138	1			T18	1		T47	2		T68	6

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal