Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.95 98.35 94.20 98.61 89.36 97.14 95.81 98.17


Total test records in report: 1101
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T126 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1689422552 May 19 01:43:43 PM PDT 24 May 19 01:43:47 PM PDT 24 566086103 ps
T1019 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1779317693 May 19 01:43:30 PM PDT 24 May 19 01:43:33 PM PDT 24 256562557 ps
T1020 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1453893881 May 19 01:43:48 PM PDT 24 May 19 01:43:51 PM PDT 24 23471107 ps
T1021 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3908869640 May 19 01:43:47 PM PDT 24 May 19 01:43:53 PM PDT 24 188910280 ps
T1022 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4078683969 May 19 01:43:48 PM PDT 24 May 19 01:43:54 PM PDT 24 233283185 ps
T142 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1590916498 May 19 01:43:42 PM PDT 24 May 19 01:43:45 PM PDT 24 42291414 ps
T1023 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2231445064 May 19 01:43:49 PM PDT 24 May 19 01:43:55 PM PDT 24 48368139 ps
T294 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.202474895 May 19 01:43:47 PM PDT 24 May 19 01:44:08 PM PDT 24 1357499895 ps
T1024 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2978961103 May 19 01:43:49 PM PDT 24 May 19 01:43:53 PM PDT 24 15210550 ps
T129 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2123174154 May 19 01:43:47 PM PDT 24 May 19 01:43:53 PM PDT 24 492227093 ps
T1025 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.721999832 May 19 01:43:40 PM PDT 24 May 19 01:43:44 PM PDT 24 1046803940 ps
T1026 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3286568362 May 19 01:43:50 PM PDT 24 May 19 01:44:05 PM PDT 24 413744717 ps
T1027 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3184576643 May 19 01:43:42 PM PDT 24 May 19 01:43:47 PM PDT 24 462271593 ps
T94 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.52108469 May 19 01:43:29 PM PDT 24 May 19 01:43:31 PM PDT 24 24539496 ps
T1028 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1371259678 May 19 01:43:42 PM PDT 24 May 19 01:43:46 PM PDT 24 25427986 ps
T1029 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.384950137 May 19 01:43:45 PM PDT 24 May 19 01:43:48 PM PDT 24 217928329 ps
T1030 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2086695968 May 19 01:43:44 PM PDT 24 May 19 01:43:50 PM PDT 24 925985085 ps
T1031 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2409343144 May 19 01:43:28 PM PDT 24 May 19 01:43:32 PM PDT 24 862960776 ps
T1032 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3451019131 May 19 01:43:43 PM PDT 24 May 19 01:43:56 PM PDT 24 1368516196 ps
T143 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3699908458 May 19 01:43:38 PM PDT 24 May 19 01:43:54 PM PDT 24 377051591 ps
T1033 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2794756707 May 19 01:43:27 PM PDT 24 May 19 01:43:29 PM PDT 24 48552887 ps
T1034 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.341493572 May 19 01:43:52 PM PDT 24 May 19 01:43:57 PM PDT 24 18651081 ps
T1035 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3729697470 May 19 01:43:50 PM PDT 24 May 19 01:43:55 PM PDT 24 45316260 ps
T144 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1508234334 May 19 01:43:45 PM PDT 24 May 19 01:43:49 PM PDT 24 115069117 ps
T293 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2363119196 May 19 01:43:27 PM PDT 24 May 19 01:43:50 PM PDT 24 829199311 ps
T1036 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1276865483 May 19 01:43:41 PM PDT 24 May 19 01:43:43 PM PDT 24 80384499 ps
T1037 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1889327474 May 19 01:43:55 PM PDT 24 May 19 01:43:59 PM PDT 24 59914684 ps
T145 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1061411225 May 19 01:43:51 PM PDT 24 May 19 01:43:57 PM PDT 24 444236185 ps
T1038 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2949958933 May 19 01:43:47 PM PDT 24 May 19 01:43:51 PM PDT 24 59852764 ps
T1039 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3748644758 May 19 01:43:52 PM PDT 24 May 19 01:43:56 PM PDT 24 39780648 ps
T1040 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3158186455 May 19 01:43:42 PM PDT 24 May 19 01:43:56 PM PDT 24 208037464 ps
T1041 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.666171925 May 19 01:43:57 PM PDT 24 May 19 01:44:01 PM PDT 24 35947220 ps
T1042 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1624872556 May 19 01:43:51 PM PDT 24 May 19 01:43:56 PM PDT 24 53604772 ps
T1043 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.242798722 May 19 01:43:48 PM PDT 24 May 19 01:43:57 PM PDT 24 100949831 ps
T1044 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2925295170 May 19 01:43:27 PM PDT 24 May 19 01:43:29 PM PDT 24 100095970 ps
T1045 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1430075303 May 19 01:43:31 PM PDT 24 May 19 01:43:32 PM PDT 24 16661882 ps
T147 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1668162143 May 19 01:43:40 PM PDT 24 May 19 01:43:42 PM PDT 24 90912524 ps
T148 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1354541479 May 19 01:43:32 PM PDT 24 May 19 01:43:34 PM PDT 24 63458322 ps
T1046 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2872144724 May 19 01:43:27 PM PDT 24 May 19 01:43:30 PM PDT 24 262015749 ps
T1047 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2386948889 May 19 01:43:51 PM PDT 24 May 19 01:43:55 PM PDT 24 79154751 ps
T1048 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2488423852 May 19 01:43:42 PM PDT 24 May 19 01:43:45 PM PDT 24 11580320 ps
T1049 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.853768138 May 19 01:43:46 PM PDT 24 May 19 01:43:49 PM PDT 24 129113553 ps
T1050 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1765536098 May 19 01:43:47 PM PDT 24 May 19 01:43:53 PM PDT 24 578490893 ps
T1051 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.665528771 May 19 01:43:47 PM PDT 24 May 19 01:43:50 PM PDT 24 29309454 ps
T1052 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1308668186 May 19 01:43:32 PM PDT 24 May 19 01:43:34 PM PDT 24 181610785 ps
T1053 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3643650313 May 19 01:43:51 PM PDT 24 May 19 01:43:56 PM PDT 24 41386249 ps
T1054 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.367838678 May 19 01:43:37 PM PDT 24 May 19 01:43:38 PM PDT 24 11455409 ps
T1055 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.630675726 May 19 01:43:36 PM PDT 24 May 19 01:43:37 PM PDT 24 25014692 ps
T1056 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1935281680 May 19 01:43:48 PM PDT 24 May 19 01:43:52 PM PDT 24 38408872 ps
T1057 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3615949781 May 19 01:43:53 PM PDT 24 May 19 01:44:00 PM PDT 24 45498963 ps
T1058 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2779153096 May 19 01:43:52 PM PDT 24 May 19 01:43:57 PM PDT 24 90315591 ps
T149 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.758802015 May 19 01:43:48 PM PDT 24 May 19 01:43:54 PM PDT 24 428514345 ps
T1059 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3462928465 May 19 01:43:45 PM PDT 24 May 19 01:43:54 PM PDT 24 1366507176 ps
T1060 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2265450950 May 19 01:43:47 PM PDT 24 May 19 01:43:49 PM PDT 24 29337567 ps
T1061 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3191017657 May 19 01:43:49 PM PDT 24 May 19 01:44:03 PM PDT 24 436283964 ps
T1062 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.754486727 May 19 01:43:44 PM PDT 24 May 19 01:43:46 PM PDT 24 43899330 ps
T1063 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2287885382 May 19 01:43:47 PM PDT 24 May 19 01:43:54 PM PDT 24 706275855 ps
T1064 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2230749513 May 19 01:43:49 PM PDT 24 May 19 01:43:55 PM PDT 24 91830728 ps
T95 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1064516706 May 19 01:43:32 PM PDT 24 May 19 01:43:34 PM PDT 24 63326291 ps
T1065 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3219488481 May 19 01:43:27 PM PDT 24 May 19 01:43:37 PM PDT 24 396082586 ps
T1066 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1323431394 May 19 01:43:53 PM PDT 24 May 19 01:43:57 PM PDT 24 24329350 ps
T1067 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1426033337 May 19 01:43:48 PM PDT 24 May 19 01:43:53 PM PDT 24 62902916 ps
T1068 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.469607 May 19 01:43:50 PM PDT 24 May 19 01:43:54 PM PDT 24 13671133 ps
T1069 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1247925080 May 19 01:43:41 PM PDT 24 May 19 01:43:44 PM PDT 24 279451871 ps
T1070 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.372210999 May 19 01:43:27 PM PDT 24 May 19 01:43:30 PM PDT 24 96369917 ps
T1071 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3951928697 May 19 01:43:47 PM PDT 24 May 19 01:43:49 PM PDT 24 30641405 ps
T1072 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2571074585 May 19 01:43:46 PM PDT 24 May 19 01:43:49 PM PDT 24 303597138 ps
T1073 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1217862649 May 19 01:43:44 PM PDT 24 May 19 01:43:46 PM PDT 24 13088434 ps
T1074 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1924008067 May 19 01:43:49 PM PDT 24 May 19 01:43:56 PM PDT 24 119493419 ps
T96 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3621748257 May 19 01:43:37 PM PDT 24 May 19 01:43:39 PM PDT 24 24596056 ps
T1075 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3027578847 May 19 01:43:28 PM PDT 24 May 19 01:43:32 PM PDT 24 413774669 ps
T1076 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3881772511 May 19 01:43:48 PM PDT 24 May 19 01:43:53 PM PDT 24 82678293 ps
T150 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4112298828 May 19 01:43:36 PM PDT 24 May 19 01:43:48 PM PDT 24 756305885 ps
T1077 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2860634277 May 19 01:43:45 PM PDT 24 May 19 01:43:49 PM PDT 24 27935180 ps
T292 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2846718072 May 19 01:43:49 PM PDT 24 May 19 01:44:09 PM PDT 24 278258634 ps
T130 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2032750080 May 19 01:43:44 PM PDT 24 May 19 01:43:48 PM PDT 24 80059908 ps
T151 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2928088456 May 19 01:43:27 PM PDT 24 May 19 01:43:45 PM PDT 24 1523689701 ps
T1078 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.149235577 May 19 01:43:41 PM PDT 24 May 19 01:43:43 PM PDT 24 72985772 ps
T1079 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3245321488 May 19 01:43:39 PM PDT 24 May 19 01:43:41 PM PDT 24 77335709 ps
T1080 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4090635303 May 19 01:43:27 PM PDT 24 May 19 01:43:31 PM PDT 24 102827044 ps
T1081 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1023017448 May 19 01:43:42 PM PDT 24 May 19 01:43:44 PM PDT 24 197927516 ps
T1082 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3725700862 May 19 01:44:01 PM PDT 24 May 19 01:44:05 PM PDT 24 100394706 ps
T1083 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2283439551 May 19 01:43:41 PM PDT 24 May 19 01:43:44 PM PDT 24 229816939 ps
T1084 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2031620393 May 19 01:43:32 PM PDT 24 May 19 01:43:33 PM PDT 24 15626524 ps
T1085 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.927021724 May 19 01:43:27 PM PDT 24 May 19 01:43:29 PM PDT 24 29371435 ps
T1086 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.159582044 May 19 01:43:34 PM PDT 24 May 19 01:43:44 PM PDT 24 770778934 ps
T1087 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.759102635 May 19 01:43:40 PM PDT 24 May 19 01:43:43 PM PDT 24 183519136 ps
T1088 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.132090915 May 19 01:43:53 PM PDT 24 May 19 01:43:58 PM PDT 24 19785974 ps
T1089 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1698285170 May 19 01:43:36 PM PDT 24 May 19 01:43:46 PM PDT 24 428057867 ps
T1090 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1310676160 May 19 01:43:26 PM PDT 24 May 19 01:43:28 PM PDT 24 147781326 ps
T1091 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1836905510 May 19 01:43:46 PM PDT 24 May 19 01:43:50 PM PDT 24 224804995 ps
T1092 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4103961964 May 19 01:43:41 PM PDT 24 May 19 01:43:45 PM PDT 24 30187426 ps
T1093 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3337415337 May 19 01:43:33 PM PDT 24 May 19 01:43:57 PM PDT 24 795835207 ps
T1094 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.516789750 May 19 01:43:47 PM PDT 24 May 19 01:43:49 PM PDT 24 37689296 ps
T1095 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2039046990 May 19 01:43:49 PM PDT 24 May 19 01:43:53 PM PDT 24 42046278 ps
T1096 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3001011694 May 19 01:43:41 PM PDT 24 May 19 01:43:47 PM PDT 24 157258411 ps
T1097 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.893662907 May 19 01:43:27 PM PDT 24 May 19 01:43:30 PM PDT 24 196505721 ps
T1098 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2359052309 May 19 01:43:44 PM PDT 24 May 19 01:44:04 PM PDT 24 872231218 ps
T1099 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4286199310 May 19 01:43:24 PM PDT 24 May 19 01:43:37 PM PDT 24 3788702968 ps
T1100 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1279567626 May 19 01:43:41 PM PDT 24 May 19 01:43:44 PM PDT 24 281867357 ps
T1101 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.784163489 May 19 01:43:52 PM PDT 24 May 19 01:43:58 PM PDT 24 401162934 ps

Test location /workspace/coverage/default/15.spi_device_flash_all.3878080331
Short name T4
Test name
Test status
Simulation time 3273548081 ps
CPU time 78.72 seconds
Started May 19 01:55:02 PM PDT 24
Finished May 19 01:56:26 PM PDT 24
Peak memory 254084 kb
Host smart-9c6df0c2-eed6-424f-9afd-38cfbee0bebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878080331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3878080331
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.245085942
Short name T18
Test name
Test status
Simulation time 27256765959 ps
CPU time 51.01 seconds
Started May 19 01:55:04 PM PDT 24
Finished May 19 01:55:59 PM PDT 24
Peak memory 250288 kb
Host smart-8f2abdc0-bf61-4461-aab4-558463235641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245085942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.245085942
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.418991453
Short name T67
Test name
Test status
Simulation time 207683978447 ps
CPU time 493.29 seconds
Started May 19 01:55:10 PM PDT 24
Finished May 19 02:03:25 PM PDT 24
Peak memory 257636 kb
Host smart-87bc92a8-f298-4bcc-8652-a7b5eab9ec77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418991453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.418991453
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.405876192
Short name T116
Test name
Test status
Simulation time 2993565465 ps
CPU time 16.53 seconds
Started May 19 01:43:29 PM PDT 24
Finished May 19 01:43:46 PM PDT 24
Peak memory 215944 kb
Host smart-a9ed8562-fbc2-4e6d-8d5f-8c84ee781e49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405876192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.405876192
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2381843086
Short name T47
Test name
Test status
Simulation time 30830352914 ps
CPU time 160.51 seconds
Started May 19 01:55:27 PM PDT 24
Finished May 19 01:58:08 PM PDT 24
Peak memory 241224 kb
Host smart-001285df-0460-4ed8-8b89-c51c3ed162ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381843086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2381843086
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2805864974
Short name T43
Test name
Test status
Simulation time 19126262830 ps
CPU time 247.71 seconds
Started May 19 01:56:11 PM PDT 24
Finished May 19 02:00:19 PM PDT 24
Peak memory 256324 kb
Host smart-9996dc48-56ed-498b-869c-b48384af8471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805864974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2805864974
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1916952146
Short name T73
Test name
Test status
Simulation time 18958346 ps
CPU time 0.75 seconds
Started May 19 01:54:17 PM PDT 24
Finished May 19 01:54:19 PM PDT 24
Peak memory 216232 kb
Host smart-90e1eed3-eb43-431d-93a0-1b5bd0917fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916952146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1916952146
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.401192001
Short name T42
Test name
Test status
Simulation time 228886408702 ps
CPU time 513.61 seconds
Started May 19 01:55:51 PM PDT 24
Finished May 19 02:04:33 PM PDT 24
Peak memory 255260 kb
Host smart-4edbd5bc-942e-431c-912f-c44072fb0815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401192001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.401192001
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.927125523
Short name T23
Test name
Test status
Simulation time 109951903949 ps
CPU time 313.63 seconds
Started May 19 01:54:55 PM PDT 24
Finished May 19 02:00:16 PM PDT 24
Peak memory 257460 kb
Host smart-d7809d9f-b9ab-4a77-a2df-31cd0db30b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927125523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.927125523
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1499600579
Short name T224
Test name
Test status
Simulation time 553134054695 ps
CPU time 1373.47 seconds
Started May 19 01:56:13 PM PDT 24
Finished May 19 02:19:07 PM PDT 24
Peak memory 306144 kb
Host smart-525b9ca5-3fed-47e9-9ae0-5054a1f65bec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499600579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1499600579
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3298434527
Short name T33
Test name
Test status
Simulation time 18202738948 ps
CPU time 120.18 seconds
Started May 19 01:54:58 PM PDT 24
Finished May 19 01:57:05 PM PDT 24
Peak memory 266712 kb
Host smart-bb837b3d-74cc-4c99-8403-f7cfa3c6ddfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298434527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3298434527
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1776388148
Short name T111
Test name
Test status
Simulation time 51614506 ps
CPU time 3.15 seconds
Started May 19 01:43:48 PM PDT 24
Finished May 19 01:43:53 PM PDT 24
Peak memory 215912 kb
Host smart-ce20d47a-0683-4e54-be00-600181eaddb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776388148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1776388148
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4156895018
Short name T136
Test name
Test status
Simulation time 1280281416 ps
CPU time 21.74 seconds
Started May 19 01:56:16 PM PDT 24
Finished May 19 01:56:39 PM PDT 24
Peak memory 225340 kb
Host smart-bc684ee3-662c-4f83-8cd1-ba8cf0d3bf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156895018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4156895018
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.463549860
Short name T92
Test name
Test status
Simulation time 47111384331 ps
CPU time 119.91 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:57:55 PM PDT 24
Peak memory 252560 kb
Host smart-a30357e7-aecd-48cc-85c7-0b1681aa25ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463549860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.463549860
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2964555254
Short name T70
Test name
Test status
Simulation time 10682562 ps
CPU time 0.7 seconds
Started May 19 01:55:05 PM PDT 24
Finished May 19 01:55:09 PM PDT 24
Peak memory 205660 kb
Host smart-05d5377f-7067-4ae8-b0fd-7cb1f2ce6d0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964555254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
964555254
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3629104611
Short name T53
Test name
Test status
Simulation time 50807447083 ps
CPU time 261.38 seconds
Started May 19 01:54:56 PM PDT 24
Finished May 19 01:59:25 PM PDT 24
Peak memory 249436 kb
Host smart-f81ca5f2-b5ba-43d2-868d-9dcb0c6440bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629104611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3629104611
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1959896619
Short name T269
Test name
Test status
Simulation time 304926539584 ps
CPU time 624.9 seconds
Started May 19 01:55:16 PM PDT 24
Finished May 19 02:05:42 PM PDT 24
Peak memory 265668 kb
Host smart-2cc683d4-2e50-49ca-866c-4ac7e05ea755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959896619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1959896619
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.52108469
Short name T94
Test name
Test status
Simulation time 24539496 ps
CPU time 1.06 seconds
Started May 19 01:43:29 PM PDT 24
Finished May 19 01:43:31 PM PDT 24
Peak memory 207252 kb
Host smart-71c6e9e4-11ee-4a6a-91d3-91a3f15d85dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52108469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_
hw_reset.52108469
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.191508814
Short name T257
Test name
Test status
Simulation time 268170177240 ps
CPU time 496.34 seconds
Started May 19 01:55:16 PM PDT 24
Finished May 19 02:03:34 PM PDT 24
Peak memory 268052 kb
Host smart-3b7b9f38-b924-4245-a1af-cedd5b23b11a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191508814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.191508814
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4283987847
Short name T38
Test name
Test status
Simulation time 50653984722 ps
CPU time 131.19 seconds
Started May 19 01:56:07 PM PDT 24
Finished May 19 01:58:19 PM PDT 24
Peak memory 265632 kb
Host smart-ae7ba995-4e8f-4d1b-8df7-4bda714b0788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283987847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4283987847
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.714654864
Short name T201
Test name
Test status
Simulation time 6403187185 ps
CPU time 77.23 seconds
Started May 19 01:56:10 PM PDT 24
Finished May 19 01:57:28 PM PDT 24
Peak memory 253568 kb
Host smart-af5ee014-2b39-4c1c-afd4-36ba2b2154dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714654864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.714654864
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2244364258
Short name T392
Test name
Test status
Simulation time 41567264 ps
CPU time 1.06 seconds
Started May 19 01:54:13 PM PDT 24
Finished May 19 01:54:16 PM PDT 24
Peak memory 216780 kb
Host smart-bfe43993-0ee5-4467-a4f6-7335a63e53ce
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244364258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2244364258
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2564080527
Short name T253
Test name
Test status
Simulation time 150729340399 ps
CPU time 377.46 seconds
Started May 19 01:54:58 PM PDT 24
Finished May 19 02:01:23 PM PDT 24
Peak memory 257324 kb
Host smart-b1307112-0586-49bc-8ff5-170940a143ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564080527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2564080527
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3412731194
Short name T162
Test name
Test status
Simulation time 19869291740 ps
CPU time 257.39 seconds
Started May 19 01:54:55 PM PDT 24
Finished May 19 01:59:20 PM PDT 24
Peak memory 273096 kb
Host smart-9cacfa87-f0bc-469b-946a-3d74a9b8b45f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412731194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3412731194
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1163913287
Short name T281
Test name
Test status
Simulation time 28043177220 ps
CPU time 108.97 seconds
Started May 19 01:55:42 PM PDT 24
Finished May 19 01:57:32 PM PDT 24
Peak memory 256312 kb
Host smart-c2e67ecd-0a7e-4fad-a11f-64c17801f8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163913287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1163913287
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1064477819
Short name T78
Test name
Test status
Simulation time 119246977 ps
CPU time 1.06 seconds
Started May 19 01:54:27 PM PDT 24
Finished May 19 01:54:29 PM PDT 24
Peak memory 235140 kb
Host smart-5c36d273-870f-4e17-bce9-68c919fe5858
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064477819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1064477819
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.991482148
Short name T254
Test name
Test status
Simulation time 184241567697 ps
CPU time 324.83 seconds
Started May 19 01:55:01 PM PDT 24
Finished May 19 02:00:31 PM PDT 24
Peak memory 253488 kb
Host smart-89d67da8-4fae-41a6-9b71-21e616ef2ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991482148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.991482148
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3657955326
Short name T41
Test name
Test status
Simulation time 10952631121 ps
CPU time 55.45 seconds
Started May 19 01:55:16 PM PDT 24
Finished May 19 01:56:13 PM PDT 24
Peak memory 249220 kb
Host smart-1a88f9bd-659b-4c2a-a354-f80c93cf69e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657955326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3657955326
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1491853888
Short name T267
Test name
Test status
Simulation time 73018697446 ps
CPU time 378.14 seconds
Started May 19 01:55:39 PM PDT 24
Finished May 19 02:01:58 PM PDT 24
Peak memory 262292 kb
Host smart-2c4473b3-476d-4396-ae87-c29702add60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491853888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1491853888
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.341536596
Short name T260
Test name
Test status
Simulation time 109263654117 ps
CPU time 552.03 seconds
Started May 19 01:55:52 PM PDT 24
Finished May 19 02:05:12 PM PDT 24
Peak memory 256724 kb
Host smart-caf0d412-f570-4d1e-97dc-d389438dcc22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341536596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.341536596
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1689422552
Short name T126
Test name
Test status
Simulation time 566086103 ps
CPU time 3.42 seconds
Started May 19 01:43:43 PM PDT 24
Finished May 19 01:43:47 PM PDT 24
Peak memory 215956 kb
Host smart-15859da8-ad8c-4479-8572-c7a2e5b57aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689422552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1689422552
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1275665908
Short name T165
Test name
Test status
Simulation time 41942173635 ps
CPU time 270.43 seconds
Started May 19 01:55:36 PM PDT 24
Finished May 19 02:00:08 PM PDT 24
Peak memory 250992 kb
Host smart-a1cdde0b-ee5c-4864-8f07-bf519e07d7e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275665908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1275665908
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.887840066
Short name T193
Test name
Test status
Simulation time 4364182228 ps
CPU time 49.82 seconds
Started May 19 01:56:30 PM PDT 24
Finished May 19 01:57:21 PM PDT 24
Peak memory 241204 kb
Host smart-a2c4edaa-fa42-4bed-a5a4-957aed71fcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887840066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.887840066
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.277459994
Short name T301
Test name
Test status
Simulation time 48670545112 ps
CPU time 122.12 seconds
Started May 19 01:54:50 PM PDT 24
Finished May 19 01:56:59 PM PDT 24
Peak memory 249404 kb
Host smart-09c580fe-a8f8-4a7a-a963-0b02acd046db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277459994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.277459994
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2260131885
Short name T3
Test name
Test status
Simulation time 31391732227 ps
CPU time 19.95 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:56:17 PM PDT 24
Peak memory 216524 kb
Host smart-34ff8e1c-738d-455b-a5bd-98d4a226619f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260131885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2260131885
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1052525748
Short name T276
Test name
Test status
Simulation time 11622612199 ps
CPU time 55.35 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:59 PM PDT 24
Peak memory 237312 kb
Host smart-0240e160-2ec9-4c4d-9651-6e9415913321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052525748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1052525748
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3667897010
Short name T315
Test name
Test status
Simulation time 2993479218 ps
CPU time 35.56 seconds
Started May 19 01:55:37 PM PDT 24
Finished May 19 01:56:14 PM PDT 24
Peak memory 236132 kb
Host smart-ba9e456e-efa3-4211-9918-ff1a3025e3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667897010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3667897010
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2856210807
Short name T274
Test name
Test status
Simulation time 30655567416 ps
CPU time 114.72 seconds
Started May 19 01:56:33 PM PDT 24
Finished May 19 01:58:29 PM PDT 24
Peak memory 254276 kb
Host smart-c7e82b8e-21cc-4214-bf9f-cd168e059308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856210807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2856210807
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2856937208
Short name T290
Test name
Test status
Simulation time 1658564019 ps
CPU time 20.77 seconds
Started May 19 01:43:29 PM PDT 24
Finished May 19 01:43:50 PM PDT 24
Peak memory 215736 kb
Host smart-873bce69-c1cc-4964-b3e8-9662351b8482
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856937208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2856937208
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1899368809
Short name T284
Test name
Test status
Simulation time 117591187674 ps
CPU time 181.87 seconds
Started May 19 01:55:09 PM PDT 24
Finished May 19 01:58:13 PM PDT 24
Peak memory 249572 kb
Host smart-cf6acf7e-e304-451e-98f6-f31c3fe5f591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899368809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1899368809
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3257317505
Short name T275
Test name
Test status
Simulation time 337552612710 ps
CPU time 568.31 seconds
Started May 19 01:55:24 PM PDT 24
Finished May 19 02:04:54 PM PDT 24
Peak memory 251864 kb
Host smart-a255bf0a-93ca-42ee-b866-f93d6c0882cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257317505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3257317505
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.481922956
Short name T186
Test name
Test status
Simulation time 8875806722 ps
CPU time 133.36 seconds
Started May 19 01:55:29 PM PDT 24
Finished May 19 01:57:43 PM PDT 24
Peak memory 253356 kb
Host smart-47edb21f-1763-4b6c-8bde-6488abec8d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481922956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.481922956
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3762252522
Short name T256
Test name
Test status
Simulation time 7074325630 ps
CPU time 173.39 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:58:53 PM PDT 24
Peak memory 288732 kb
Host smart-be2b18c0-4c8b-46d2-924b-ed679934b5c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762252522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3762252522
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3535225266
Short name T106
Test name
Test status
Simulation time 1015380329 ps
CPU time 5.3 seconds
Started May 19 01:55:07 PM PDT 24
Finished May 19 01:55:15 PM PDT 24
Peak memory 234128 kb
Host smart-479ff890-36d7-4cc8-b200-764405b70996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535225266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3535225266
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2123174154
Short name T129
Test name
Test status
Simulation time 492227093 ps
CPU time 4.08 seconds
Started May 19 01:43:47 PM PDT 24
Finished May 19 01:43:53 PM PDT 24
Peak memory 215824 kb
Host smart-019986f0-2f96-4f6a-9ca7-44a55a0ee244
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123174154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2123174154
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2846718072
Short name T292
Test name
Test status
Simulation time 278258634 ps
CPU time 17.03 seconds
Started May 19 01:43:49 PM PDT 24
Finished May 19 01:44:09 PM PDT 24
Peak memory 215792 kb
Host smart-0b839713-efe3-4970-82b4-3fe27caf7bab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846718072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2846718072
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2553244257
Short name T519
Test name
Test status
Simulation time 3422420648 ps
CPU time 47.08 seconds
Started May 19 01:54:58 PM PDT 24
Finished May 19 01:55:52 PM PDT 24
Peak memory 232724 kb
Host smart-dcffd0c8-9675-4670-bc43-567d8548beb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553244257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2553244257
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1355629385
Short name T268
Test name
Test status
Simulation time 4949263343 ps
CPU time 97.95 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:56:37 PM PDT 24
Peak memory 264428 kb
Host smart-a65bd0b6-2429-438e-9b6b-fbe39a50b16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355629385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1355629385
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.4276195556
Short name T198
Test name
Test status
Simulation time 26746911054 ps
CPU time 83.48 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:57:24 PM PDT 24
Peak memory 263396 kb
Host smart-8e3c39c1-5843-4e66-9991-bc61542d7978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276195556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.4276195556
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.967008641
Short name T36
Test name
Test status
Simulation time 121670751440 ps
CPU time 76.01 seconds
Started May 19 01:55:37 PM PDT 24
Finished May 19 01:56:54 PM PDT 24
Peak memory 241016 kb
Host smart-e912e428-c4a1-44ad-95df-210bf1896547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967008641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.967008641
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1064516706
Short name T95
Test name
Test status
Simulation time 63326291 ps
CPU time 1.22 seconds
Started May 19 01:43:32 PM PDT 24
Finished May 19 01:43:34 PM PDT 24
Peak memory 207352 kb
Host smart-f9a279b0-84a1-4000-aea8-e5b37cc3a0ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064516706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1064516706
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3219488481
Short name T1065
Test name
Test status
Simulation time 396082586 ps
CPU time 8.61 seconds
Started May 19 01:43:27 PM PDT 24
Finished May 19 01:43:37 PM PDT 24
Peak memory 207356 kb
Host smart-81757bdf-fe20-427f-ba3c-a0b943c405b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219488481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3219488481
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4286199310
Short name T1099
Test name
Test status
Simulation time 3788702968 ps
CPU time 12.14 seconds
Started May 19 01:43:24 PM PDT 24
Finished May 19 01:43:37 PM PDT 24
Peak memory 207748 kb
Host smart-98bd6df5-61a0-4af3-b6df-0061a2850b5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286199310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.4286199310
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.927021724
Short name T1085
Test name
Test status
Simulation time 29371435 ps
CPU time 0.95 seconds
Started May 19 01:43:27 PM PDT 24
Finished May 19 01:43:29 PM PDT 24
Peak memory 207308 kb
Host smart-c1412061-09a0-4816-9641-0ea3649b3afc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927021724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.927021724
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3633118797
Short name T131
Test name
Test status
Simulation time 275887687 ps
CPU time 3.48 seconds
Started May 19 01:43:24 PM PDT 24
Finished May 19 01:43:28 PM PDT 24
Peak memory 218020 kb
Host smart-ca21edeb-d5f9-40ac-8f8f-6c70718936c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633118797 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3633118797
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.893662907
Short name T1097
Test name
Test status
Simulation time 196505721 ps
CPU time 1.27 seconds
Started May 19 01:43:27 PM PDT 24
Finished May 19 01:43:30 PM PDT 24
Peak memory 207484 kb
Host smart-c3e3917d-60a4-40f9-82a1-8868df99ce92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893662907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.893662907
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3143411663
Short name T990
Test name
Test status
Simulation time 15888821 ps
CPU time 0.81 seconds
Started May 19 01:43:25 PM PDT 24
Finished May 19 01:43:27 PM PDT 24
Peak memory 204244 kb
Host smart-8de47792-681d-4818-9bcc-89e27f53b2e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143411663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
143411663
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3027578847
Short name T1075
Test name
Test status
Simulation time 413774669 ps
CPU time 2.2 seconds
Started May 19 01:43:28 PM PDT 24
Finished May 19 01:43:32 PM PDT 24
Peak memory 215660 kb
Host smart-2c0335e3-598a-4a07-97e4-ce92facf8f69
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027578847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3027578847
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2031620393
Short name T1084
Test name
Test status
Simulation time 15626524 ps
CPU time 0.65 seconds
Started May 19 01:43:32 PM PDT 24
Finished May 19 01:43:33 PM PDT 24
Peak memory 203800 kb
Host smart-4c249143-1cf5-486b-90dc-7c407d9f88ca
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031620393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2031620393
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3098907459
Short name T167
Test name
Test status
Simulation time 264641075 ps
CPU time 2.91 seconds
Started May 19 01:43:25 PM PDT 24
Finished May 19 01:43:29 PM PDT 24
Peak memory 215784 kb
Host smart-566842e9-b8af-49a9-b348-664582466240
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098907459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3098907459
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2409343144
Short name T1031
Test name
Test status
Simulation time 862960776 ps
CPU time 2.82 seconds
Started May 19 01:43:28 PM PDT 24
Finished May 19 01:43:32 PM PDT 24
Peak memory 215752 kb
Host smart-d0d25e8e-c001-483e-b726-2363630af465
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409343144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
409343144
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2928088456
Short name T151
Test name
Test status
Simulation time 1523689701 ps
CPU time 15.75 seconds
Started May 19 01:43:27 PM PDT 24
Finished May 19 01:43:45 PM PDT 24
Peak memory 207524 kb
Host smart-577de5c4-fc7a-4dc7-ae58-a1a102d494ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928088456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2928088456
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4080669535
Short name T146
Test name
Test status
Simulation time 627685120 ps
CPU time 12.95 seconds
Started May 19 01:43:28 PM PDT 24
Finished May 19 01:43:42 PM PDT 24
Peak memory 207384 kb
Host smart-316ead5b-3893-4443-8193-5373614dc2b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080669535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.4080669535
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2110673864
Short name T992
Test name
Test status
Simulation time 47661950 ps
CPU time 1.54 seconds
Started May 19 01:43:26 PM PDT 24
Finished May 19 01:43:28 PM PDT 24
Peak memory 215824 kb
Host smart-fa308750-7238-4667-9886-a10bb59535ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110673864 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2110673864
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.372210999
Short name T1070
Test name
Test status
Simulation time 96369917 ps
CPU time 1.92 seconds
Started May 19 01:43:27 PM PDT 24
Finished May 19 01:43:30 PM PDT 24
Peak memory 215748 kb
Host smart-bf0409e0-575b-4e93-a0e9-43f99ed43144
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372210999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.372210999
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1430075303
Short name T1045
Test name
Test status
Simulation time 16661882 ps
CPU time 0.74 seconds
Started May 19 01:43:31 PM PDT 24
Finished May 19 01:43:32 PM PDT 24
Peak memory 204208 kb
Host smart-65f81ab6-f86e-4514-9b89-77a3a24cfdc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430075303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
430075303
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1310676160
Short name T1090
Test name
Test status
Simulation time 147781326 ps
CPU time 1.61 seconds
Started May 19 01:43:26 PM PDT 24
Finished May 19 01:43:28 PM PDT 24
Peak memory 215856 kb
Host smart-26391df4-1dc7-4b2c-ab84-d9974157f456
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310676160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1310676160
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1366092943
Short name T984
Test name
Test status
Simulation time 12254061 ps
CPU time 0.65 seconds
Started May 19 01:43:26 PM PDT 24
Finished May 19 01:43:28 PM PDT 24
Peak memory 203856 kb
Host smart-8f806ccd-22d5-4a96-a3e0-012f5f0c5f1c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366092943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1366092943
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4090635303
Short name T1080
Test name
Test status
Simulation time 102827044 ps
CPU time 1.83 seconds
Started May 19 01:43:27 PM PDT 24
Finished May 19 01:43:31 PM PDT 24
Peak memory 216012 kb
Host smart-bfe6f912-92e9-4b87-a6b4-221c60773ef6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090635303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.4090635303
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2925295170
Short name T1044
Test name
Test status
Simulation time 100095970 ps
CPU time 1.45 seconds
Started May 19 01:43:27 PM PDT 24
Finished May 19 01:43:29 PM PDT 24
Peak memory 215876 kb
Host smart-b4c83bf6-f1b4-4c66-b58d-ff6bbf9e2534
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925295170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
925295170
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2363119196
Short name T293
Test name
Test status
Simulation time 829199311 ps
CPU time 21.74 seconds
Started May 19 01:43:27 PM PDT 24
Finished May 19 01:43:50 PM PDT 24
Peak memory 216380 kb
Host smart-5eddf566-682f-4d66-a3e9-aa0458585350
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363119196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2363119196
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3109265106
Short name T112
Test name
Test status
Simulation time 25224920 ps
CPU time 1.84 seconds
Started May 19 01:43:41 PM PDT 24
Finished May 19 01:43:45 PM PDT 24
Peak memory 215964 kb
Host smart-26ee40ba-2f33-4a4d-9068-10c5f4afee64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109265106 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3109265106
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4103961964
Short name T1092
Test name
Test status
Simulation time 30187426 ps
CPU time 1.97 seconds
Started May 19 01:43:41 PM PDT 24
Finished May 19 01:43:45 PM PDT 24
Peak memory 207472 kb
Host smart-a51928c3-55dc-4a18-8147-ebc8a95e1911
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103961964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
4103961964
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1935281680
Short name T1056
Test name
Test status
Simulation time 38408872 ps
CPU time 0.74 seconds
Started May 19 01:43:48 PM PDT 24
Finished May 19 01:43:52 PM PDT 24
Peak memory 203964 kb
Host smart-8c90707d-6440-4099-a8de-db291cceabfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935281680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1935281680
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1279567626
Short name T1100
Test name
Test status
Simulation time 281867357 ps
CPU time 1.86 seconds
Started May 19 01:43:41 PM PDT 24
Finished May 19 01:43:44 PM PDT 24
Peak memory 216436 kb
Host smart-56cf5eb2-f7ff-41a5-b006-cda2110760e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279567626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1279567626
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.784163489
Short name T1101
Test name
Test status
Simulation time 401162934 ps
CPU time 2.73 seconds
Started May 19 01:43:52 PM PDT 24
Finished May 19 01:43:58 PM PDT 24
Peak memory 215852 kb
Host smart-93afc63c-9c47-4715-8e3a-3b6dc0b60257
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784163489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.784163489
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2135885352
Short name T291
Test name
Test status
Simulation time 815681218 ps
CPU time 20.97 seconds
Started May 19 01:43:39 PM PDT 24
Finished May 19 01:44:01 PM PDT 24
Peak memory 215728 kb
Host smart-36610ade-907d-4681-b586-25ade7049141
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135885352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2135885352
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2442235513
Short name T123
Test name
Test status
Simulation time 426386037 ps
CPU time 3.55 seconds
Started May 19 01:43:41 PM PDT 24
Finished May 19 01:43:47 PM PDT 24
Peak memory 218544 kb
Host smart-b17f4f80-249d-4709-9775-b821da84b3ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442235513 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2442235513
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3881772511
Short name T1076
Test name
Test status
Simulation time 82678293 ps
CPU time 2.11 seconds
Started May 19 01:43:48 PM PDT 24
Finished May 19 01:43:53 PM PDT 24
Peak memory 215608 kb
Host smart-f93c55d2-77c8-4785-b303-f3bcf85d8695
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881772511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3881772511
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1217862649
Short name T1073
Test name
Test status
Simulation time 13088434 ps
CPU time 0.69 seconds
Started May 19 01:43:44 PM PDT 24
Finished May 19 01:43:46 PM PDT 24
Peak memory 204228 kb
Host smart-b919ec03-8296-4c13-9c74-671d3c6e9878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217862649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1217862649
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3001011694
Short name T1096
Test name
Test status
Simulation time 157258411 ps
CPU time 4.24 seconds
Started May 19 01:43:41 PM PDT 24
Finished May 19 01:43:47 PM PDT 24
Peak memory 215740 kb
Host smart-a406b0c8-0984-4f70-901c-77dc84876693
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001011694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3001011694
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4217679873
Short name T120
Test name
Test status
Simulation time 54346593 ps
CPU time 2.89 seconds
Started May 19 01:43:41 PM PDT 24
Finished May 19 01:43:45 PM PDT 24
Peak memory 215912 kb
Host smart-3e7d5989-ab8e-4327-9097-9034bfe669ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217679873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
4217679873
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3451019131
Short name T1032
Test name
Test status
Simulation time 1368516196 ps
CPU time 12.58 seconds
Started May 19 01:43:43 PM PDT 24
Finished May 19 01:43:56 PM PDT 24
Peak memory 215852 kb
Host smart-67c5752c-4706-4ef6-b984-fc5bfe16fd87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451019131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3451019131
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.384950137
Short name T1029
Test name
Test status
Simulation time 217928329 ps
CPU time 1.78 seconds
Started May 19 01:43:45 PM PDT 24
Finished May 19 01:43:48 PM PDT 24
Peak memory 215856 kb
Host smart-2c6aa6d2-c710-414a-88cd-8bccddbd14f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384950137 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.384950137
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2504938952
Short name T137
Test name
Test status
Simulation time 612280293 ps
CPU time 2.38 seconds
Started May 19 01:43:44 PM PDT 24
Finished May 19 01:43:48 PM PDT 24
Peak memory 207616 kb
Host smart-444598ed-c625-4a7f-a83b-449b79c4cc8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504938952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2504938952
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2265450950
Short name T1060
Test name
Test status
Simulation time 29337567 ps
CPU time 0.75 seconds
Started May 19 01:43:47 PM PDT 24
Finished May 19 01:43:49 PM PDT 24
Peak memory 204264 kb
Host smart-4a917f41-ae37-41fb-9cb3-831c00858a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265450950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2265450950
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4244307402
Short name T177
Test name
Test status
Simulation time 495527337 ps
CPU time 2.84 seconds
Started May 19 01:43:44 PM PDT 24
Finished May 19 01:43:48 PM PDT 24
Peak memory 215704 kb
Host smart-f8790c66-2800-4f51-87da-bb452f6f2af8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244307402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.4244307402
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3286568362
Short name T1026
Test name
Test status
Simulation time 413744717 ps
CPU time 12.15 seconds
Started May 19 01:43:50 PM PDT 24
Finished May 19 01:44:05 PM PDT 24
Peak memory 216136 kb
Host smart-bf376ef9-dff9-4fa9-b7cb-fffc477038ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286568362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3286568362
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1836905510
Short name T1091
Test name
Test status
Simulation time 224804995 ps
CPU time 2.74 seconds
Started May 19 01:43:46 PM PDT 24
Finished May 19 01:43:50 PM PDT 24
Peak memory 217520 kb
Host smart-bb5fdce4-c38d-46eb-850e-3edbc79d9982
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836905510 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1836905510
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2230749513
Short name T1064
Test name
Test status
Simulation time 91830728 ps
CPU time 2.57 seconds
Started May 19 01:43:49 PM PDT 24
Finished May 19 01:43:55 PM PDT 24
Peak memory 207440 kb
Host smart-7dd8477b-401c-498c-b1f4-0dd6ce7aad03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230749513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2230749513
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2978961103
Short name T1024
Test name
Test status
Simulation time 15210550 ps
CPU time 0.74 seconds
Started May 19 01:43:49 PM PDT 24
Finished May 19 01:43:53 PM PDT 24
Peak memory 203936 kb
Host smart-eafb44bf-f7cc-4b05-8765-31ef4d3ed044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978961103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2978961103
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.38059436
Short name T176
Test name
Test status
Simulation time 512774254 ps
CPU time 2.92 seconds
Started May 19 01:43:52 PM PDT 24
Finished May 19 01:44:00 PM PDT 24
Peak memory 215732 kb
Host smart-aff1cdc6-428d-4c03-9bab-f89bec953b93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38059436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sp
i_device_same_csr_outstanding.38059436
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4078683969
Short name T1022
Test name
Test status
Simulation time 233283185 ps
CPU time 3.14 seconds
Started May 19 01:43:48 PM PDT 24
Finished May 19 01:43:54 PM PDT 24
Peak memory 216068 kb
Host smart-2c1e82d2-4558-40e1-a0d8-9fa19496eb8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078683969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
4078683969
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3191017657
Short name T1061
Test name
Test status
Simulation time 436283964 ps
CPU time 11.91 seconds
Started May 19 01:43:49 PM PDT 24
Finished May 19 01:44:03 PM PDT 24
Peak memory 215892 kb
Host smart-a2a62b36-e179-464e-8e84-aa7506674e80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191017657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3191017657
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1731803962
Short name T998
Test name
Test status
Simulation time 111384540 ps
CPU time 3.56 seconds
Started May 19 01:43:46 PM PDT 24
Finished May 19 01:43:51 PM PDT 24
Peak memory 217392 kb
Host smart-a2c0d54e-0a5e-4905-a56f-da93447c63aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731803962 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1731803962
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.853768138
Short name T1049
Test name
Test status
Simulation time 129113553 ps
CPU time 1.97 seconds
Started May 19 01:43:46 PM PDT 24
Finished May 19 01:43:49 PM PDT 24
Peak memory 207480 kb
Host smart-1fba4900-af62-42fc-9614-3ff7f728f3f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853768138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.853768138
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2114821933
Short name T1003
Test name
Test status
Simulation time 14460220 ps
CPU time 0.7 seconds
Started May 19 01:43:48 PM PDT 24
Finished May 19 01:43:52 PM PDT 24
Peak memory 203868 kb
Host smart-b84dc208-6991-444f-946c-8fcfd9616fab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114821933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2114821933
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3833520731
Short name T1017
Test name
Test status
Simulation time 203894785 ps
CPU time 3.07 seconds
Started May 19 01:43:49 PM PDT 24
Finished May 19 01:43:54 PM PDT 24
Peak memory 215728 kb
Host smart-cb2f34f7-6a2d-4818-8933-4863e4f82ff7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833520731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3833520731
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1703292671
Short name T122
Test name
Test status
Simulation time 698010606 ps
CPU time 5.01 seconds
Started May 19 01:43:51 PM PDT 24
Finished May 19 01:44:00 PM PDT 24
Peak memory 215956 kb
Host smart-e7df9c1e-912b-44ac-9dcc-9970e3d18f6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703292671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1703292671
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2128505704
Short name T1000
Test name
Test status
Simulation time 1056940359 ps
CPU time 7.48 seconds
Started May 19 01:43:46 PM PDT 24
Finished May 19 01:43:55 PM PDT 24
Peak memory 215912 kb
Host smart-a0634ad5-98a2-4e2a-8b72-bbccfb2b20f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128505704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2128505704
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2860634277
Short name T1077
Test name
Test status
Simulation time 27935180 ps
CPU time 1.78 seconds
Started May 19 01:43:45 PM PDT 24
Finished May 19 01:43:49 PM PDT 24
Peak memory 216844 kb
Host smart-9e60a107-fb19-48dd-8b8a-327ad8412c85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860634277 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2860634277
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1426033337
Short name T1067
Test name
Test status
Simulation time 62902916 ps
CPU time 1.87 seconds
Started May 19 01:43:48 PM PDT 24
Finished May 19 01:43:53 PM PDT 24
Peak memory 207488 kb
Host smart-ae787ee4-74bc-4dd9-b0be-e06e1d4a5008
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426033337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1426033337
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.754486727
Short name T1062
Test name
Test status
Simulation time 43899330 ps
CPU time 0.74 seconds
Started May 19 01:43:44 PM PDT 24
Finished May 19 01:43:46 PM PDT 24
Peak memory 203956 kb
Host smart-fc538efe-c836-49ee-8187-f68d0151c27a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754486727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.754486727
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3303884570
Short name T986
Test name
Test status
Simulation time 46287165 ps
CPU time 2.77 seconds
Started May 19 01:43:46 PM PDT 24
Finished May 19 01:43:51 PM PDT 24
Peak memory 215800 kb
Host smart-4baf4c47-152a-44b5-84d1-5dc678ec6f5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303884570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3303884570
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2240765367
Short name T993
Test name
Test status
Simulation time 90752541 ps
CPU time 2.33 seconds
Started May 19 01:43:50 PM PDT 24
Finished May 19 01:43:56 PM PDT 24
Peak memory 215884 kb
Host smart-811cd389-de54-46f0-b700-4e414ceb5590
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240765367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2240765367
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3141075252
Short name T117
Test name
Test status
Simulation time 1046093984 ps
CPU time 6.7 seconds
Started May 19 01:43:51 PM PDT 24
Finished May 19 01:44:01 PM PDT 24
Peak memory 215816 kb
Host smart-c6c2d59a-dafb-450e-a754-b0ebeb981cb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141075252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3141075252
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3729697470
Short name T1035
Test name
Test status
Simulation time 45316260 ps
CPU time 1.71 seconds
Started May 19 01:43:50 PM PDT 24
Finished May 19 01:43:55 PM PDT 24
Peak memory 215864 kb
Host smart-ede53b31-24cf-48bc-9d99-115652dba0ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729697470 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3729697470
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2949958933
Short name T1038
Test name
Test status
Simulation time 59852764 ps
CPU time 1.94 seconds
Started May 19 01:43:47 PM PDT 24
Finished May 19 01:43:51 PM PDT 24
Peak memory 215672 kb
Host smart-715d3894-3b4d-4dd2-983b-549c48c465bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949958933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2949958933
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1317701790
Short name T1010
Test name
Test status
Simulation time 43286959 ps
CPU time 0.71 seconds
Started May 19 01:43:50 PM PDT 24
Finished May 19 01:43:53 PM PDT 24
Peak memory 204008 kb
Host smart-6a45006d-faa0-4b61-b5e6-cf9cdce0eca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317701790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1317701790
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2287885382
Short name T1063
Test name
Test status
Simulation time 706275855 ps
CPU time 4.04 seconds
Started May 19 01:43:47 PM PDT 24
Finished May 19 01:43:54 PM PDT 24
Peak memory 215716 kb
Host smart-ec9fa7f1-f7f4-4c41-9e8e-c429123db23b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287885382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2287885382
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2468181541
Short name T121
Test name
Test status
Simulation time 62256427 ps
CPU time 3.92 seconds
Started May 19 01:43:50 PM PDT 24
Finished May 19 01:43:56 PM PDT 24
Peak memory 215812 kb
Host smart-46b3cd13-da76-4b5e-9283-c11533d2fa0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468181541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2468181541
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3462928465
Short name T1059
Test name
Test status
Simulation time 1366507176 ps
CPU time 7.86 seconds
Started May 19 01:43:45 PM PDT 24
Finished May 19 01:43:54 PM PDT 24
Peak memory 215848 kb
Host smart-76af0880-bd33-44af-827f-11dca89ab8d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462928465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3462928465
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2231445064
Short name T1023
Test name
Test status
Simulation time 48368139 ps
CPU time 2.77 seconds
Started May 19 01:43:49 PM PDT 24
Finished May 19 01:43:55 PM PDT 24
Peak memory 216764 kb
Host smart-82514833-377f-42c2-8753-07233d572f3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231445064 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2231445064
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.758802015
Short name T149
Test name
Test status
Simulation time 428514345 ps
CPU time 2.8 seconds
Started May 19 01:43:48 PM PDT 24
Finished May 19 01:43:54 PM PDT 24
Peak memory 207624 kb
Host smart-995e1fa0-c0ef-4b3c-8768-40d8fab8228f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758802015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.758802015
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.516789750
Short name T1094
Test name
Test status
Simulation time 37689296 ps
CPU time 0.72 seconds
Started May 19 01:43:47 PM PDT 24
Finished May 19 01:43:49 PM PDT 24
Peak memory 203900 kb
Host smart-36b79d28-6c81-45b1-ab04-20dfdccbadb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516789750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.516789750
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1765536098
Short name T1050
Test name
Test status
Simulation time 578490893 ps
CPU time 4.3 seconds
Started May 19 01:43:47 PM PDT 24
Finished May 19 01:43:53 PM PDT 24
Peak memory 215776 kb
Host smart-44612cc9-b311-47cd-8939-d80125558697
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765536098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1765536098
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.202474895
Short name T294
Test name
Test status
Simulation time 1357499895 ps
CPU time 19.04 seconds
Started May 19 01:43:47 PM PDT 24
Finished May 19 01:44:08 PM PDT 24
Peak memory 215752 kb
Host smart-dc593dad-7157-44a5-b3e7-48f966f12fd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202474895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.202474895
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.840668256
Short name T128
Test name
Test status
Simulation time 589129465 ps
CPU time 3.66 seconds
Started May 19 01:43:51 PM PDT 24
Finished May 19 01:43:58 PM PDT 24
Peak memory 218612 kb
Host smart-d0323791-3b89-47dd-8a5b-2fdfea0725d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840668256 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.840668256
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1061411225
Short name T145
Test name
Test status
Simulation time 444236185 ps
CPU time 2.49 seconds
Started May 19 01:43:51 PM PDT 24
Finished May 19 01:43:57 PM PDT 24
Peak memory 215712 kb
Host smart-399a858c-2bdb-452d-8bd6-db18f6680a3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061411225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1061411225
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4151686915
Short name T1007
Test name
Test status
Simulation time 46426579 ps
CPU time 0.74 seconds
Started May 19 01:43:50 PM PDT 24
Finished May 19 01:43:54 PM PDT 24
Peak memory 203968 kb
Host smart-f372b369-d3bb-4c03-af1f-fd8daf454584
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151686915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
4151686915
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1924008067
Short name T1074
Test name
Test status
Simulation time 119493419 ps
CPU time 3.79 seconds
Started May 19 01:43:49 PM PDT 24
Finished May 19 01:43:56 PM PDT 24
Peak memory 215764 kb
Host smart-211909cd-8728-4e21-b2d2-c9780c71d07d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924008067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1924008067
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3533795414
Short name T133
Test name
Test status
Simulation time 139030116 ps
CPU time 3.53 seconds
Started May 19 01:43:47 PM PDT 24
Finished May 19 01:43:52 PM PDT 24
Peak memory 217492 kb
Host smart-763f0e57-3d83-4422-8e40-7b310f6e9d3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533795414 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3533795414
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3951928697
Short name T1071
Test name
Test status
Simulation time 30641405 ps
CPU time 1.28 seconds
Started May 19 01:43:47 PM PDT 24
Finished May 19 01:43:49 PM PDT 24
Peak memory 207472 kb
Host smart-354f2b7a-e9bf-43ad-baa7-153098c1ca74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951928697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3951928697
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2039046990
Short name T1095
Test name
Test status
Simulation time 42046278 ps
CPU time 0.71 seconds
Started May 19 01:43:49 PM PDT 24
Finished May 19 01:43:53 PM PDT 24
Peak memory 204248 kb
Host smart-0bd794b0-395e-4c4a-bacd-6ecd6a4b86c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039046990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2039046990
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3908869640
Short name T1021
Test name
Test status
Simulation time 188910280 ps
CPU time 4.04 seconds
Started May 19 01:43:47 PM PDT 24
Finished May 19 01:43:53 PM PDT 24
Peak memory 215688 kb
Host smart-cc962ef5-e90e-4d9f-b770-aed0371b04ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908869640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3908869640
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1756887864
Short name T125
Test name
Test status
Simulation time 23876786 ps
CPU time 1.72 seconds
Started May 19 01:43:47 PM PDT 24
Finished May 19 01:43:51 PM PDT 24
Peak memory 215840 kb
Host smart-d987ef75-2e24-4078-9e71-9c58cdf57086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756887864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1756887864
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.242798722
Short name T1043
Test name
Test status
Simulation time 100949831 ps
CPU time 6.63 seconds
Started May 19 01:43:48 PM PDT 24
Finished May 19 01:43:57 PM PDT 24
Peak memory 215960 kb
Host smart-d5711631-9240-4c9a-b340-be64b673e1b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242798722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.242798722
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.159582044
Short name T1086
Test name
Test status
Simulation time 770778934 ps
CPU time 8.96 seconds
Started May 19 01:43:34 PM PDT 24
Finished May 19 01:43:44 PM PDT 24
Peak memory 215952 kb
Host smart-919728d0-e940-4bc6-8efa-781fefb04e4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159582044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.159582044
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3337415337
Short name T1093
Test name
Test status
Simulation time 795835207 ps
CPU time 22.97 seconds
Started May 19 01:43:33 PM PDT 24
Finished May 19 01:43:57 PM PDT 24
Peak memory 215660 kb
Host smart-f3c49a5f-7e4e-4bd2-b22d-6761830f9b4a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337415337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3337415337
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1308668186
Short name T1052
Test name
Test status
Simulation time 181610785 ps
CPU time 1.67 seconds
Started May 19 01:43:32 PM PDT 24
Finished May 19 01:43:34 PM PDT 24
Peak memory 215788 kb
Host smart-d59c8230-46ae-48ae-adcc-e8221f18f3ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308668186 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1308668186
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4260148687
Short name T140
Test name
Test status
Simulation time 97265286 ps
CPU time 2.74 seconds
Started May 19 01:43:30 PM PDT 24
Finished May 19 01:43:33 PM PDT 24
Peak memory 207560 kb
Host smart-040507bb-299b-44d6-b318-1220b039799f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260148687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
260148687
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2794756707
Short name T1033
Test name
Test status
Simulation time 48552887 ps
CPU time 0.7 seconds
Started May 19 01:43:27 PM PDT 24
Finished May 19 01:43:29 PM PDT 24
Peak memory 203876 kb
Host smart-751c8787-8921-46cb-9ff3-00b5dadbb49c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794756707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
794756707
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1354541479
Short name T148
Test name
Test status
Simulation time 63458322 ps
CPU time 1.55 seconds
Started May 19 01:43:32 PM PDT 24
Finished May 19 01:43:34 PM PDT 24
Peak memory 215700 kb
Host smart-282c0bfa-5c6b-4641-b2ea-30412687af1d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354541479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1354541479
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3445215918
Short name T983
Test name
Test status
Simulation time 13226519 ps
CPU time 0.67 seconds
Started May 19 01:43:30 PM PDT 24
Finished May 19 01:43:31 PM PDT 24
Peak memory 203848 kb
Host smart-c9ceb753-62bb-4eff-936b-34bde3b880ac
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445215918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3445215918
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1779317693
Short name T1019
Test name
Test status
Simulation time 256562557 ps
CPU time 2.84 seconds
Started May 19 01:43:30 PM PDT 24
Finished May 19 01:43:33 PM PDT 24
Peak memory 216012 kb
Host smart-907c2680-7a06-447a-9198-74cfde82ea51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779317693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1779317693
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2872144724
Short name T1046
Test name
Test status
Simulation time 262015749 ps
CPU time 2.06 seconds
Started May 19 01:43:27 PM PDT 24
Finished May 19 01:43:30 PM PDT 24
Peak memory 215896 kb
Host smart-c3d53661-6a4c-4c54-945f-1942e74881a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872144724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
872144724
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3412205888
Short name T1011
Test name
Test status
Simulation time 15808118 ps
CPU time 0.75 seconds
Started May 19 01:43:47 PM PDT 24
Finished May 19 01:43:50 PM PDT 24
Peak memory 204188 kb
Host smart-f470084b-a641-4a8a-b3cf-65ea998eca6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412205888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3412205888
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2864190204
Short name T1016
Test name
Test status
Simulation time 13920473 ps
CPU time 0.75 seconds
Started May 19 01:43:52 PM PDT 24
Finished May 19 01:43:56 PM PDT 24
Peak memory 204196 kb
Host smart-251daa45-c29d-486b-bdd2-14d16eb1b27d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864190204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2864190204
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.150406959
Short name T997
Test name
Test status
Simulation time 14981275 ps
CPU time 0.74 seconds
Started May 19 01:43:50 PM PDT 24
Finished May 19 01:43:54 PM PDT 24
Peak memory 204188 kb
Host smart-81f1649a-e050-4a3c-8aa1-96d659bbd7da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150406959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.150406959
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3321971085
Short name T1014
Test name
Test status
Simulation time 50083807 ps
CPU time 0.76 seconds
Started May 19 01:43:52 PM PDT 24
Finished May 19 01:43:57 PM PDT 24
Peak memory 203892 kb
Host smart-78a6ca36-2401-48e6-bfeb-fc01008037d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321971085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3321971085
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2824485199
Short name T994
Test name
Test status
Simulation time 20244152 ps
CPU time 0.73 seconds
Started May 19 01:43:52 PM PDT 24
Finished May 19 01:43:57 PM PDT 24
Peak memory 204280 kb
Host smart-aa003a01-92d9-4818-a1bb-5829ef6dbe38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824485199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2824485199
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2779153096
Short name T1058
Test name
Test status
Simulation time 90315591 ps
CPU time 0.72 seconds
Started May 19 01:43:52 PM PDT 24
Finished May 19 01:43:57 PM PDT 24
Peak memory 204260 kb
Host smart-ebdd367c-7535-46dd-96ed-796ca007d629
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779153096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2779153096
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2022071473
Short name T1004
Test name
Test status
Simulation time 13585632 ps
CPU time 0.78 seconds
Started May 19 01:43:53 PM PDT 24
Finished May 19 01:43:58 PM PDT 24
Peak memory 204196 kb
Host smart-dbff9a20-7649-42db-a721-ee9b3ca21048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022071473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2022071473
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.469607
Short name T1068
Test name
Test status
Simulation time 13671133 ps
CPU time 0.69 seconds
Started May 19 01:43:50 PM PDT 24
Finished May 19 01:43:54 PM PDT 24
Peak memory 203920 kb
Host smart-cb643d4a-fa29-4a90-9c8f-78ced884f92e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.469607
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3490521469
Short name T987
Test name
Test status
Simulation time 75289183 ps
CPU time 0.69 seconds
Started May 19 01:43:53 PM PDT 24
Finished May 19 01:43:58 PM PDT 24
Peak memory 203920 kb
Host smart-8f3a609b-83d7-4ecc-a3e5-40071fcdfe05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490521469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3490521469
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.504939455
Short name T1018
Test name
Test status
Simulation time 13870221 ps
CPU time 0.67 seconds
Started May 19 01:43:51 PM PDT 24
Finished May 19 01:43:55 PM PDT 24
Peak memory 203940 kb
Host smart-c7599032-c969-4adc-be34-66ccac7ecc42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504939455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.504939455
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1698285170
Short name T1089
Test name
Test status
Simulation time 428057867 ps
CPU time 9.42 seconds
Started May 19 01:43:36 PM PDT 24
Finished May 19 01:43:46 PM PDT 24
Peak memory 207500 kb
Host smart-619d39cb-0a7b-4a4c-aacd-0aefae5e0cc0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698285170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1698285170
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3362927080
Short name T1012
Test name
Test status
Simulation time 4169455353 ps
CPU time 25.4 seconds
Started May 19 01:43:45 PM PDT 24
Finished May 19 01:44:12 PM PDT 24
Peak memory 207496 kb
Host smart-e9923adf-20df-474b-90e4-8fc3c5d1b239
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362927080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3362927080
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3621748257
Short name T96
Test name
Test status
Simulation time 24596056 ps
CPU time 1.33 seconds
Started May 19 01:43:37 PM PDT 24
Finished May 19 01:43:39 PM PDT 24
Peak memory 207504 kb
Host smart-fd195f33-904a-47f0-b996-a0a3693b972a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621748257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3621748257
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3643913887
Short name T127
Test name
Test status
Simulation time 40365234 ps
CPU time 2.64 seconds
Started May 19 01:43:34 PM PDT 24
Finished May 19 01:43:38 PM PDT 24
Peak memory 216164 kb
Host smart-9e701d64-7a54-4435-b03e-64817808fe2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643913887 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3643913887
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1364039431
Short name T141
Test name
Test status
Simulation time 95169756 ps
CPU time 2.55 seconds
Started May 19 01:43:34 PM PDT 24
Finished May 19 01:43:37 PM PDT 24
Peak memory 215716 kb
Host smart-7f186056-4558-41c0-a282-49119f6bb6e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364039431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
364039431
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1135715253
Short name T989
Test name
Test status
Simulation time 14064807 ps
CPU time 0.7 seconds
Started May 19 01:43:34 PM PDT 24
Finished May 19 01:43:35 PM PDT 24
Peak memory 203884 kb
Host smart-c1319546-3a1d-44f8-80a9-3563ba107ad6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135715253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
135715253
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2708386097
Short name T139
Test name
Test status
Simulation time 171528183 ps
CPU time 1.63 seconds
Started May 19 01:43:39 PM PDT 24
Finished May 19 01:43:41 PM PDT 24
Peak memory 215776 kb
Host smart-efb37ef9-22fb-443e-b4c7-ec797e69d2ed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708386097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2708386097
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.630675726
Short name T1055
Test name
Test status
Simulation time 25014692 ps
CPU time 0.65 seconds
Started May 19 01:43:36 PM PDT 24
Finished May 19 01:43:37 PM PDT 24
Peak memory 203864 kb
Host smart-ba0cf3a5-45d2-41a3-a3b4-58b77c34aaec
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630675726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.630675726
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3339683321
Short name T988
Test name
Test status
Simulation time 27588143 ps
CPU time 1.64 seconds
Started May 19 01:43:45 PM PDT 24
Finished May 19 01:43:48 PM PDT 24
Peak memory 215376 kb
Host smart-22196db7-8dba-4f94-9582-8e0ac35459bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339683321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3339683321
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1267935499
Short name T119
Test name
Test status
Simulation time 58854901 ps
CPU time 1.72 seconds
Started May 19 01:43:34 PM PDT 24
Finished May 19 01:43:36 PM PDT 24
Peak memory 217888 kb
Host smart-963551dc-1d58-4eb2-8459-65b60fe502bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267935499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
267935499
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3275824910
Short name T113
Test name
Test status
Simulation time 1781819408 ps
CPU time 12.07 seconds
Started May 19 01:43:31 PM PDT 24
Finished May 19 01:43:44 PM PDT 24
Peak memory 216008 kb
Host smart-a9bc6aa8-5985-43f9-8e0d-450badc7e4b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275824910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3275824910
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3421259183
Short name T995
Test name
Test status
Simulation time 37192243 ps
CPU time 0.69 seconds
Started May 19 01:43:51 PM PDT 24
Finished May 19 01:43:55 PM PDT 24
Peak memory 203892 kb
Host smart-0d1803db-0b7a-4dc1-b777-76343afd2fe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421259183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3421259183
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4141565554
Short name T1013
Test name
Test status
Simulation time 40734379 ps
CPU time 0.7 seconds
Started May 19 01:43:54 PM PDT 24
Finished May 19 01:43:58 PM PDT 24
Peak memory 203984 kb
Host smart-c7b81421-dda3-4a17-8d2a-ed15ebc6bef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141565554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4141565554
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2535886842
Short name T1006
Test name
Test status
Simulation time 41885715 ps
CPU time 0.69 seconds
Started May 19 01:44:02 PM PDT 24
Finished May 19 01:44:06 PM PDT 24
Peak memory 203900 kb
Host smart-df5a6c2d-0b0f-42c0-a3b8-c59857fb8992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535886842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2535886842
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1323431394
Short name T1066
Test name
Test status
Simulation time 24329350 ps
CPU time 0.71 seconds
Started May 19 01:43:53 PM PDT 24
Finished May 19 01:43:57 PM PDT 24
Peak memory 204192 kb
Host smart-d0406816-c9a0-4efc-9c2c-4725e7fae2a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323431394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1323431394
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1608339468
Short name T1015
Test name
Test status
Simulation time 19423324 ps
CPU time 0.79 seconds
Started May 19 01:43:54 PM PDT 24
Finished May 19 01:43:58 PM PDT 24
Peak memory 203992 kb
Host smart-7ac6a8d4-d831-4158-8ece-74988d75bad6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608339468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1608339468
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.152829949
Short name T1002
Test name
Test status
Simulation time 38729523 ps
CPU time 0.75 seconds
Started May 19 01:43:52 PM PDT 24
Finished May 19 01:43:57 PM PDT 24
Peak memory 204196 kb
Host smart-785b013a-34a9-4c52-962f-762e81848936
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152829949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.152829949
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3643650313
Short name T1053
Test name
Test status
Simulation time 41386249 ps
CPU time 0.72 seconds
Started May 19 01:43:51 PM PDT 24
Finished May 19 01:43:56 PM PDT 24
Peak memory 204472 kb
Host smart-8f872b0f-896f-4f39-80ff-b8a8f263b983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643650313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3643650313
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1889327474
Short name T1037
Test name
Test status
Simulation time 59914684 ps
CPU time 0.76 seconds
Started May 19 01:43:55 PM PDT 24
Finished May 19 01:43:59 PM PDT 24
Peak memory 203960 kb
Host smart-51b0aee6-662f-4356-9424-b5864b016730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889327474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1889327474
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1624872556
Short name T1042
Test name
Test status
Simulation time 53604772 ps
CPU time 0.72 seconds
Started May 19 01:43:51 PM PDT 24
Finished May 19 01:43:56 PM PDT 24
Peak memory 204036 kb
Host smart-668afadd-db10-4cbd-9c27-1f0d9919da4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624872556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1624872556
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3725700862
Short name T1082
Test name
Test status
Simulation time 100394706 ps
CPU time 0.67 seconds
Started May 19 01:44:01 PM PDT 24
Finished May 19 01:44:05 PM PDT 24
Peak memory 203900 kb
Host smart-250e6f6b-ff9f-401f-9d69-4d422a49ae7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725700862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3725700862
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3699908458
Short name T143
Test name
Test status
Simulation time 377051591 ps
CPU time 15.09 seconds
Started May 19 01:43:38 PM PDT 24
Finished May 19 01:43:54 PM PDT 24
Peak memory 215712 kb
Host smart-c3b8c05f-bfb9-4105-8274-19b28381a636
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699908458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3699908458
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4112298828
Short name T150
Test name
Test status
Simulation time 756305885 ps
CPU time 11.24 seconds
Started May 19 01:43:36 PM PDT 24
Finished May 19 01:43:48 PM PDT 24
Peak memory 207188 kb
Host smart-0d8f4d3b-f825-4547-b2e4-4dcdf9c3ed7b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112298828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.4112298828
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.689623585
Short name T93
Test name
Test status
Simulation time 129236992 ps
CPU time 1.2 seconds
Started May 19 01:43:37 PM PDT 24
Finished May 19 01:43:39 PM PDT 24
Peak memory 207452 kb
Host smart-a4931796-283b-4795-95d5-fbe695e70647
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689623585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.689623585
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.721999832
Short name T1025
Test name
Test status
Simulation time 1046803940 ps
CPU time 2.8 seconds
Started May 19 01:43:40 PM PDT 24
Finished May 19 01:43:44 PM PDT 24
Peak memory 217064 kb
Host smart-af5288b8-9472-4ee7-8c3d-4a019ddeb2ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721999832 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.721999832
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1668162143
Short name T147
Test name
Test status
Simulation time 90912524 ps
CPU time 1.36 seconds
Started May 19 01:43:40 PM PDT 24
Finished May 19 01:43:42 PM PDT 24
Peak memory 215752 kb
Host smart-31001c41-0679-4d4f-b323-9168129ed277
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668162143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
668162143
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1068957286
Short name T999
Test name
Test status
Simulation time 14778395 ps
CPU time 0.71 seconds
Started May 19 01:43:44 PM PDT 24
Finished May 19 01:43:46 PM PDT 24
Peak memory 203868 kb
Host smart-6f7c03cc-3dba-42aa-b3cf-c2b2d4c4b8c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068957286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
068957286
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3245321488
Short name T1079
Test name
Test status
Simulation time 77335709 ps
CPU time 1.67 seconds
Started May 19 01:43:39 PM PDT 24
Finished May 19 01:43:41 PM PDT 24
Peak memory 215748 kb
Host smart-71334032-e718-400e-8318-d016b5944d76
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245321488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3245321488
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.367838678
Short name T1054
Test name
Test status
Simulation time 11455409 ps
CPU time 0.67 seconds
Started May 19 01:43:37 PM PDT 24
Finished May 19 01:43:38 PM PDT 24
Peak memory 204184 kb
Host smart-a6ed0bac-2609-485c-8562-c1ab7803d018
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367838678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.367838678
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2571074585
Short name T1072
Test name
Test status
Simulation time 303597138 ps
CPU time 2.04 seconds
Started May 19 01:43:46 PM PDT 24
Finished May 19 01:43:49 PM PDT 24
Peak memory 215672 kb
Host smart-9f0d42a5-bcc4-42bb-8fb4-bb3546a8dc08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571074585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2571074585
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1869528896
Short name T118
Test name
Test status
Simulation time 139980000 ps
CPU time 3.39 seconds
Started May 19 01:43:45 PM PDT 24
Finished May 19 01:43:50 PM PDT 24
Peak memory 215588 kb
Host smart-bac08f19-424c-4a33-9e9e-28afe372bbe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869528896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
869528896
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2445314750
Short name T135
Test name
Test status
Simulation time 606991805 ps
CPU time 18.51 seconds
Started May 19 01:43:44 PM PDT 24
Finished May 19 01:44:04 PM PDT 24
Peak memory 215652 kb
Host smart-752c2f8f-6a4f-4844-bb8b-9eb400b9bae3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445314750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2445314750
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3327851533
Short name T991
Test name
Test status
Simulation time 43693715 ps
CPU time 0.74 seconds
Started May 19 01:43:51 PM PDT 24
Finished May 19 01:43:56 PM PDT 24
Peak memory 204208 kb
Host smart-42d1081c-c384-4358-95b8-4e2ef4f141a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327851533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3327851533
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.666171925
Short name T1041
Test name
Test status
Simulation time 35947220 ps
CPU time 0.73 seconds
Started May 19 01:43:57 PM PDT 24
Finished May 19 01:44:01 PM PDT 24
Peak memory 204016 kb
Host smart-1f62d967-c252-4cb6-a086-bc0b980294d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666171925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.666171925
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1707435047
Short name T1001
Test name
Test status
Simulation time 16886470 ps
CPU time 0.75 seconds
Started May 19 01:43:51 PM PDT 24
Finished May 19 01:43:56 PM PDT 24
Peak memory 203936 kb
Host smart-a70db8a9-0816-4fb8-8e18-03b453572163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707435047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1707435047
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.751194649
Short name T985
Test name
Test status
Simulation time 13506603 ps
CPU time 0.72 seconds
Started May 19 01:43:52 PM PDT 24
Finished May 19 01:43:56 PM PDT 24
Peak memory 203984 kb
Host smart-52d8e7f9-5a45-4c79-98fb-ffa434370beb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751194649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.751194649
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.341493572
Short name T1034
Test name
Test status
Simulation time 18651081 ps
CPU time 0.81 seconds
Started May 19 01:43:52 PM PDT 24
Finished May 19 01:43:57 PM PDT 24
Peak memory 203980 kb
Host smart-85384f72-d89c-47c3-96cc-1685e1affc1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341493572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.341493572
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3748644758
Short name T1039
Test name
Test status
Simulation time 39780648 ps
CPU time 0.68 seconds
Started May 19 01:43:52 PM PDT 24
Finished May 19 01:43:56 PM PDT 24
Peak memory 203884 kb
Host smart-961769c9-c359-4ead-b907-16c2a12db619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748644758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3748644758
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2177134701
Short name T982
Test name
Test status
Simulation time 83667129 ps
CPU time 0.7 seconds
Started May 19 01:43:51 PM PDT 24
Finished May 19 01:43:56 PM PDT 24
Peak memory 203900 kb
Host smart-c39054a0-b621-41e6-84b3-478802a9e6a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177134701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2177134701
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2386948889
Short name T1047
Test name
Test status
Simulation time 79154751 ps
CPU time 0.75 seconds
Started May 19 01:43:51 PM PDT 24
Finished May 19 01:43:55 PM PDT 24
Peak memory 203976 kb
Host smart-90a318ad-a642-4754-9031-2733a05311b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386948889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2386948889
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3545983222
Short name T1005
Test name
Test status
Simulation time 11501638 ps
CPU time 0.69 seconds
Started May 19 01:44:03 PM PDT 24
Finished May 19 01:44:07 PM PDT 24
Peak memory 203900 kb
Host smart-1ab09c2d-f852-4c00-bc27-44d66712949d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545983222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3545983222
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.132090915
Short name T1088
Test name
Test status
Simulation time 19785974 ps
CPU time 0.74 seconds
Started May 19 01:43:53 PM PDT 24
Finished May 19 01:43:58 PM PDT 24
Peak memory 203960 kb
Host smart-49c8e351-9a1a-49c4-8f8a-c25b09aaca66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132090915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.132090915
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1371259678
Short name T1028
Test name
Test status
Simulation time 25427986 ps
CPU time 1.74 seconds
Started May 19 01:43:42 PM PDT 24
Finished May 19 01:43:46 PM PDT 24
Peak memory 216872 kb
Host smart-21aa799a-2a43-47ec-85db-0d1ececb79cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371259678 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1371259678
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1508234334
Short name T144
Test name
Test status
Simulation time 115069117 ps
CPU time 2.72 seconds
Started May 19 01:43:45 PM PDT 24
Finished May 19 01:43:49 PM PDT 24
Peak memory 215700 kb
Host smart-f9252b55-c28f-4f89-8409-ffd6e58a7de5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508234334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
508234334
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1276865483
Short name T1036
Test name
Test status
Simulation time 80384499 ps
CPU time 0.74 seconds
Started May 19 01:43:41 PM PDT 24
Finished May 19 01:43:43 PM PDT 24
Peak memory 204244 kb
Host smart-e08f3fe5-45dc-446e-b469-3da1df9c6189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276865483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
276865483
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1247925080
Short name T1069
Test name
Test status
Simulation time 279451871 ps
CPU time 1.88 seconds
Started May 19 01:43:41 PM PDT 24
Finished May 19 01:43:44 PM PDT 24
Peak memory 215804 kb
Host smart-f22f00b1-0065-4a17-84a7-466faec72a62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247925080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1247925080
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2283439551
Short name T1083
Test name
Test status
Simulation time 229816939 ps
CPU time 2.08 seconds
Started May 19 01:43:41 PM PDT 24
Finished May 19 01:43:44 PM PDT 24
Peak memory 215744 kb
Host smart-633c4dce-8645-4346-b85a-e353079307e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283439551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
283439551
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3428812595
Short name T178
Test name
Test status
Simulation time 2155262574 ps
CPU time 14.65 seconds
Started May 19 01:43:41 PM PDT 24
Finished May 19 01:43:56 PM PDT 24
Peak memory 215928 kb
Host smart-73b45e0f-890d-4092-8454-2965e20add5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428812595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3428812595
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1370602801
Short name T1009
Test name
Test status
Simulation time 42075378 ps
CPU time 1.56 seconds
Started May 19 01:43:41 PM PDT 24
Finished May 19 01:43:44 PM PDT 24
Peak memory 215784 kb
Host smart-0a7ebd45-dd10-46d3-ac27-69dd58d231ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370602801 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1370602801
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2064942555
Short name T138
Test name
Test status
Simulation time 122842066 ps
CPU time 1.21 seconds
Started May 19 01:43:40 PM PDT 24
Finished May 19 01:43:42 PM PDT 24
Peak memory 207444 kb
Host smart-e9102df7-54b9-4c86-8e98-1b019ba7499c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064942555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
064942555
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2488423852
Short name T1048
Test name
Test status
Simulation time 11580320 ps
CPU time 0.8 seconds
Started May 19 01:43:42 PM PDT 24
Finished May 19 01:43:45 PM PDT 24
Peak memory 204280 kb
Host smart-06a71fff-6c82-4b1d-a9d6-4ea9137071eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488423852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
488423852
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2133593839
Short name T1008
Test name
Test status
Simulation time 261953214 ps
CPU time 1.85 seconds
Started May 19 01:43:45 PM PDT 24
Finished May 19 01:43:49 PM PDT 24
Peak memory 207608 kb
Host smart-4e4d347c-1382-4faf-a0cb-f1aded6bcddf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133593839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2133593839
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.108177596
Short name T114
Test name
Test status
Simulation time 302311998 ps
CPU time 3.88 seconds
Started May 19 01:43:52 PM PDT 24
Finished May 19 01:44:00 PM PDT 24
Peak memory 215788 kb
Host smart-168c6183-e46a-4dc4-bac2-521b68751f2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108177596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.108177596
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2359052309
Short name T1098
Test name
Test status
Simulation time 872231218 ps
CPU time 19.07 seconds
Started May 19 01:43:44 PM PDT 24
Finished May 19 01:44:04 PM PDT 24
Peak memory 216316 kb
Host smart-61195c21-3a6f-4a82-b172-425389c96346
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359052309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2359052309
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.759102635
Short name T1087
Test name
Test status
Simulation time 183519136 ps
CPU time 1.5 seconds
Started May 19 01:43:40 PM PDT 24
Finished May 19 01:43:43 PM PDT 24
Peak memory 215928 kb
Host smart-dcb66dea-7eac-467a-a13c-507244589680
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759102635 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.759102635
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.149235577
Short name T1078
Test name
Test status
Simulation time 72985772 ps
CPU time 1.47 seconds
Started May 19 01:43:41 PM PDT 24
Finished May 19 01:43:43 PM PDT 24
Peak memory 215696 kb
Host smart-b797e496-bc28-4cb3-a213-208136290fe5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149235577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.149235577
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.665528771
Short name T1051
Test name
Test status
Simulation time 29309454 ps
CPU time 0.78 seconds
Started May 19 01:43:47 PM PDT 24
Finished May 19 01:43:50 PM PDT 24
Peak memory 203912 kb
Host smart-cf98999f-5d85-4a82-a745-e0382d3a19c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665528771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.665528771
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1379049787
Short name T168
Test name
Test status
Simulation time 98566459 ps
CPU time 2.66 seconds
Started May 19 01:43:45 PM PDT 24
Finished May 19 01:43:49 PM PDT 24
Peak memory 215780 kb
Host smart-8df8ed84-9ce6-4be6-a107-4747068a78b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379049787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1379049787
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2032750080
Short name T130
Test name
Test status
Simulation time 80059908 ps
CPU time 2.74 seconds
Started May 19 01:43:44 PM PDT 24
Finished May 19 01:43:48 PM PDT 24
Peak memory 215924 kb
Host smart-ed00bcd2-56c7-4f03-a13b-dade625faac3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032750080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
032750080
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1353982916
Short name T132
Test name
Test status
Simulation time 359754069 ps
CPU time 7.88 seconds
Started May 19 01:43:46 PM PDT 24
Finished May 19 01:43:55 PM PDT 24
Peak memory 215748 kb
Host smart-9199e46a-28c7-427f-ab3e-0789cb671ae8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353982916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1353982916
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2642511703
Short name T115
Test name
Test status
Simulation time 455753099 ps
CPU time 3.27 seconds
Started May 19 01:43:40 PM PDT 24
Finished May 19 01:43:43 PM PDT 24
Peak memory 217756 kb
Host smart-b3e3c102-4e5d-4a54-bbf1-809fb20b9905
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642511703 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2642511703
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1023017448
Short name T1081
Test name
Test status
Simulation time 197927516 ps
CPU time 1.15 seconds
Started May 19 01:43:42 PM PDT 24
Finished May 19 01:43:44 PM PDT 24
Peak memory 207488 kb
Host smart-90545091-13bc-4d69-80f3-32117292f2ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023017448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
023017448
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1695884939
Short name T996
Test name
Test status
Simulation time 41061673 ps
CPU time 0.74 seconds
Started May 19 01:43:41 PM PDT 24
Finished May 19 01:43:43 PM PDT 24
Peak memory 204196 kb
Host smart-c2a7f808-7130-4010-be92-959c63851f62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695884939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
695884939
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3615949781
Short name T1057
Test name
Test status
Simulation time 45498963 ps
CPU time 2.79 seconds
Started May 19 01:43:53 PM PDT 24
Finished May 19 01:44:00 PM PDT 24
Peak memory 215688 kb
Host smart-c980d73a-0b63-4238-9e83-54750becae06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615949781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3615949781
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2891407799
Short name T124
Test name
Test status
Simulation time 76848272 ps
CPU time 1.87 seconds
Started May 19 01:43:42 PM PDT 24
Finished May 19 01:43:45 PM PDT 24
Peak memory 216012 kb
Host smart-03e1d112-2ee4-4fb2-958c-00620fe8a118
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891407799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
891407799
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3158186455
Short name T1040
Test name
Test status
Simulation time 208037464 ps
CPU time 12.68 seconds
Started May 19 01:43:42 PM PDT 24
Finished May 19 01:43:56 PM PDT 24
Peak memory 215728 kb
Host smart-cbcebcac-2431-4ac9-9d56-75a5382a4b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158186455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3158186455
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3184576643
Short name T1027
Test name
Test status
Simulation time 462271593 ps
CPU time 3.55 seconds
Started May 19 01:43:42 PM PDT 24
Finished May 19 01:43:47 PM PDT 24
Peak memory 216820 kb
Host smart-5e09f493-3f4c-466e-bbd3-e8a61186cba4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184576643 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3184576643
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1590916498
Short name T142
Test name
Test status
Simulation time 42291414 ps
CPU time 1.38 seconds
Started May 19 01:43:42 PM PDT 24
Finished May 19 01:43:45 PM PDT 24
Peak memory 215764 kb
Host smart-416f7106-7a9f-4f9f-84c9-d582ccb2bd3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590916498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
590916498
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1453893881
Short name T1020
Test name
Test status
Simulation time 23471107 ps
CPU time 0.75 seconds
Started May 19 01:43:48 PM PDT 24
Finished May 19 01:43:51 PM PDT 24
Peak memory 203852 kb
Host smart-81a145d7-2e85-496a-b456-a0cb9fcc9602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453893881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
453893881
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4093362203
Short name T182
Test name
Test status
Simulation time 275790738 ps
CPU time 1.88 seconds
Started May 19 01:43:40 PM PDT 24
Finished May 19 01:43:43 PM PDT 24
Peak memory 215748 kb
Host smart-c5a80694-6ede-41ff-b63b-af696fc701ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093362203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4093362203
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2086695968
Short name T1030
Test name
Test status
Simulation time 925985085 ps
CPU time 5.43 seconds
Started May 19 01:43:44 PM PDT 24
Finished May 19 01:43:50 PM PDT 24
Peak memory 215856 kb
Host smart-af527e1f-a4bc-4de0-996c-343da690360c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086695968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
086695968
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.877303958
Short name T134
Test name
Test status
Simulation time 878531561 ps
CPU time 12.08 seconds
Started May 19 01:43:42 PM PDT 24
Finished May 19 01:43:56 PM PDT 24
Peak memory 215752 kb
Host smart-d95e0502-a134-4428-b6e6-f419530e70f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877303958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.877303958
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3370008990
Short name T571
Test name
Test status
Simulation time 46001633 ps
CPU time 0.74 seconds
Started May 19 01:54:19 PM PDT 24
Finished May 19 01:54:20 PM PDT 24
Peak memory 205712 kb
Host smart-64f4b754-fc18-40e2-83d9-3cc6ae06ad1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370008990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
370008990
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3958756672
Short name T852
Test name
Test status
Simulation time 1515958938 ps
CPU time 8.59 seconds
Started May 19 01:54:23 PM PDT 24
Finished May 19 01:54:32 PM PDT 24
Peak memory 219844 kb
Host smart-b4b819f0-bd83-425d-94a7-37e290af7f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958756672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3958756672
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2527300898
Short name T389
Test name
Test status
Simulation time 21643904 ps
CPU time 0.79 seconds
Started May 19 01:54:14 PM PDT 24
Finished May 19 01:54:17 PM PDT 24
Peak memory 206668 kb
Host smart-b948839e-30af-4e2d-9b02-a8bd07461faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527300898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2527300898
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4175165730
Short name T562
Test name
Test status
Simulation time 15719399475 ps
CPU time 29.38 seconds
Started May 19 01:54:22 PM PDT 24
Finished May 19 01:54:52 PM PDT 24
Peak memory 241036 kb
Host smart-3a795906-e088-4a65-9712-f126d56911db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175165730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4175165730
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.335510634
Short name T591
Test name
Test status
Simulation time 8863959266 ps
CPU time 45.18 seconds
Started May 19 01:54:38 PM PDT 24
Finished May 19 01:55:24 PM PDT 24
Peak memory 240412 kb
Host smart-a99844bb-72ca-404b-af2f-5527a91cb39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335510634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.335510634
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1881608760
Short name T745
Test name
Test status
Simulation time 9626554336 ps
CPU time 61.91 seconds
Started May 19 01:54:24 PM PDT 24
Finished May 19 01:55:32 PM PDT 24
Peak memory 255552 kb
Host smart-14c8891f-29ca-4a98-8ab1-db96d61ad2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881608760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1881608760
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.772806147
Short name T546
Test name
Test status
Simulation time 1912815088 ps
CPU time 5.48 seconds
Started May 19 01:54:19 PM PDT 24
Finished May 19 01:54:25 PM PDT 24
Peak memory 232764 kb
Host smart-dab332bc-8a78-4846-818c-b27bdc4f97f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772806147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.772806147
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1920745173
Short name T309
Test name
Test status
Simulation time 6020847719 ps
CPU time 26.53 seconds
Started May 19 01:54:35 PM PDT 24
Finished May 19 01:55:02 PM PDT 24
Peak memory 219576 kb
Host smart-a40494e0-6635-49ed-99bb-3a6f045b1584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920745173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1920745173
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2542713607
Short name T327
Test name
Test status
Simulation time 905339137 ps
CPU time 13.18 seconds
Started May 19 01:54:18 PM PDT 24
Finished May 19 01:54:32 PM PDT 24
Peak memory 220192 kb
Host smart-3130e719-f713-4cca-8e6a-b81a46be44a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542713607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2542713607
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3030360725
Short name T957
Test name
Test status
Simulation time 32300677 ps
CPU time 2.31 seconds
Started May 19 01:54:33 PM PDT 24
Finished May 19 01:54:36 PM PDT 24
Peak memory 221324 kb
Host smart-70bc1b42-4a99-4346-95e8-da5158964e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030360725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3030360725
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1831419229
Short name T597
Test name
Test status
Simulation time 12985288799 ps
CPU time 38.85 seconds
Started May 19 01:54:43 PM PDT 24
Finished May 19 01:55:24 PM PDT 24
Peak memory 232160 kb
Host smart-93bf723d-0006-479d-bea5-4ef5a954761a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831419229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1831419229
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1812603653
Short name T814
Test name
Test status
Simulation time 3821424180 ps
CPU time 9.23 seconds
Started May 19 01:54:35 PM PDT 24
Finished May 19 01:54:45 PM PDT 24
Peak memory 222488 kb
Host smart-dbf167a2-12ec-40f6-bb67-5c70c8b4cc07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1812603653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1812603653
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.931877751
Short name T414
Test name
Test status
Simulation time 193104558 ps
CPU time 1.04 seconds
Started May 19 01:54:38 PM PDT 24
Finished May 19 01:54:40 PM PDT 24
Peak memory 206696 kb
Host smart-5773a430-b970-4694-8f2b-b5cb0d53b8f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931877751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.931877751
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1700721011
Short name T701
Test name
Test status
Simulation time 18373155369 ps
CPU time 22.99 seconds
Started May 19 01:54:14 PM PDT 24
Finished May 19 01:54:38 PM PDT 24
Peak memory 216612 kb
Host smart-56c15e0f-688b-419b-9517-17cdb776aa8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700721011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1700721011
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2940286743
Short name T97
Test name
Test status
Simulation time 192251039 ps
CPU time 1.28 seconds
Started May 19 01:54:16 PM PDT 24
Finished May 19 01:54:18 PM PDT 24
Peak memory 207796 kb
Host smart-8f70bb7a-c851-4f74-acd8-634d1936640f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940286743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2940286743
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4173260506
Short name T964
Test name
Test status
Simulation time 148504939 ps
CPU time 2.4 seconds
Started May 19 01:54:21 PM PDT 24
Finished May 19 01:54:24 PM PDT 24
Peak memory 216364 kb
Host smart-a32c9921-da9f-4927-b039-ceccd15d5bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173260506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4173260506
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1238884327
Short name T451
Test name
Test status
Simulation time 148624715 ps
CPU time 0.81 seconds
Started May 19 01:54:43 PM PDT 24
Finished May 19 01:54:46 PM PDT 24
Peak memory 205816 kb
Host smart-ebdce22c-161d-4c39-bedb-d98f7d30e428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238884327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1238884327
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3113283513
Short name T551
Test name
Test status
Simulation time 17515069139 ps
CPU time 30.79 seconds
Started May 19 01:54:23 PM PDT 24
Finished May 19 01:54:55 PM PDT 24
Peak memory 229572 kb
Host smart-8e15d80a-9bbc-41b7-8ea1-a06fa6aff497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113283513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3113283513
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.214448423
Short name T434
Test name
Test status
Simulation time 25087506 ps
CPU time 0.7 seconds
Started May 19 01:54:36 PM PDT 24
Finished May 19 01:54:38 PM PDT 24
Peak memory 204744 kb
Host smart-7a7d620e-8977-41d5-a7e6-cbb95b58d8bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214448423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.214448423
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3457144948
Short name T107
Test name
Test status
Simulation time 344624514 ps
CPU time 2.28 seconds
Started May 19 01:54:22 PM PDT 24
Finished May 19 01:54:24 PM PDT 24
Peak memory 218488 kb
Host smart-0dd8878a-3505-47df-b153-ab1a988f402d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457144948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3457144948
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.146631176
Short name T921
Test name
Test status
Simulation time 20244504 ps
CPU time 0.84 seconds
Started May 19 01:54:25 PM PDT 24
Finished May 19 01:54:27 PM PDT 24
Peak memory 206804 kb
Host smart-351544cf-5e22-445b-8e95-636e06907303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146631176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.146631176
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1059262691
Short name T794
Test name
Test status
Simulation time 90458761970 ps
CPU time 178.5 seconds
Started May 19 01:54:47 PM PDT 24
Finished May 19 01:57:50 PM PDT 24
Peak memory 257444 kb
Host smart-e057c376-a838-4db4-b786-73f44ba1d7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059262691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1059262691
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3637919304
Short name T365
Test name
Test status
Simulation time 33257192 ps
CPU time 0.9 seconds
Started May 19 01:54:28 PM PDT 24
Finished May 19 01:54:30 PM PDT 24
Peak memory 217112 kb
Host smart-5b36d776-2024-48cc-a9cc-853f60ed0a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637919304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3637919304
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3618177073
Short name T353
Test name
Test status
Simulation time 168719975091 ps
CPU time 397.6 seconds
Started May 19 01:54:39 PM PDT 24
Finished May 19 02:01:17 PM PDT 24
Peak memory 250404 kb
Host smart-bfd96ba0-d1f6-4ac1-80ea-1c349e9ef753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618177073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3618177073
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1557441545
Short name T741
Test name
Test status
Simulation time 221489358 ps
CPU time 3.22 seconds
Started May 19 01:54:28 PM PDT 24
Finished May 19 01:54:32 PM PDT 24
Peak memory 224532 kb
Host smart-672a16ab-791c-4e22-aa50-5a4d28d31c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557441545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1557441545
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1715269197
Short name T217
Test name
Test status
Simulation time 2076729688 ps
CPU time 6.15 seconds
Started May 19 01:54:20 PM PDT 24
Finished May 19 01:54:26 PM PDT 24
Peak memory 218596 kb
Host smart-b47fc3d9-418d-4606-b84d-625284849119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715269197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1715269197
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1068666616
Short name T784
Test name
Test status
Simulation time 8472503579 ps
CPU time 14.62 seconds
Started May 19 01:54:28 PM PDT 24
Finished May 19 01:54:43 PM PDT 24
Peak memory 249036 kb
Host smart-d8f8c7be-df4d-4905-8849-bd00ed5532a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068666616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1068666616
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2817010109
Short name T547
Test name
Test status
Simulation time 70998648 ps
CPU time 1.06 seconds
Started May 19 01:54:40 PM PDT 24
Finished May 19 01:54:42 PM PDT 24
Peak memory 216736 kb
Host smart-88f6a365-530c-428e-9a8c-26a922a194f3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817010109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2817010109
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3268645231
Short name T341
Test name
Test status
Simulation time 1485963379 ps
CPU time 6.24 seconds
Started May 19 01:54:20 PM PDT 24
Finished May 19 01:54:27 PM PDT 24
Peak memory 238768 kb
Host smart-8265764b-0cbb-42a6-ba46-8a5569fc9bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268645231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3268645231
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2715429373
Short name T690
Test name
Test status
Simulation time 1179594867 ps
CPU time 5.62 seconds
Started May 19 01:54:36 PM PDT 24
Finished May 19 01:54:43 PM PDT 24
Peak memory 229628 kb
Host smart-1790aa18-6916-4130-80cd-27e3175051ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715429373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2715429373
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2691743795
Short name T428
Test name
Test status
Simulation time 5277713879 ps
CPU time 13.02 seconds
Started May 19 01:54:35 PM PDT 24
Finished May 19 01:54:50 PM PDT 24
Peak memory 220268 kb
Host smart-51aba772-3912-499d-b709-1d4d10ceb423
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2691743795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2691743795
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.516120484
Short name T79
Test name
Test status
Simulation time 62177461 ps
CPU time 1.11 seconds
Started May 19 01:54:22 PM PDT 24
Finished May 19 01:54:23 PM PDT 24
Peak memory 235120 kb
Host smart-23d6b350-1599-433a-a0c0-209e65ecc662
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516120484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.516120484
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.4874870
Short name T762
Test name
Test status
Simulation time 73293387 ps
CPU time 0.98 seconds
Started May 19 01:54:44 PM PDT 24
Finished May 19 01:54:47 PM PDT 24
Peak memory 206692 kb
Host smart-11c297ab-a091-4e4a-b740-e3cb65d81fa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4874870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_a
ll.4874870
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3602558098
Short name T965
Test name
Test status
Simulation time 4409600894 ps
CPU time 29.64 seconds
Started May 19 01:54:20 PM PDT 24
Finished May 19 01:54:51 PM PDT 24
Peak memory 216508 kb
Host smart-03b9455a-658d-41f5-a84d-413e615a1cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602558098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3602558098
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1354840589
Short name T832
Test name
Test status
Simulation time 879203943 ps
CPU time 3.02 seconds
Started May 19 01:54:20 PM PDT 24
Finished May 19 01:54:23 PM PDT 24
Peak memory 207880 kb
Host smart-5b470c9f-9e8d-4cb3-b4ae-d3c6aabd8ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354840589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1354840589
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2020967443
Short name T514
Test name
Test status
Simulation time 88670059 ps
CPU time 1.13 seconds
Started May 19 01:54:20 PM PDT 24
Finished May 19 01:54:22 PM PDT 24
Peak memory 207972 kb
Host smart-589e1ac3-3fbc-4c4b-beb4-d734c2ee7c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020967443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2020967443
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.591992050
Short name T583
Test name
Test status
Simulation time 284351425 ps
CPU time 0.97 seconds
Started May 19 01:54:22 PM PDT 24
Finished May 19 01:54:23 PM PDT 24
Peak memory 205804 kb
Host smart-89b4013e-a511-464e-99af-351a1fe23977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591992050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.591992050
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1884550470
Short name T743
Test name
Test status
Simulation time 6550966261 ps
CPU time 19.85 seconds
Started May 19 01:54:21 PM PDT 24
Finished May 19 01:54:42 PM PDT 24
Peak memory 221368 kb
Host smart-53ae2ad9-1483-4ed1-8d47-470f04d420da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884550470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1884550470
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2777276088
Short name T368
Test name
Test status
Simulation time 107300702 ps
CPU time 0.69 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:54:56 PM PDT 24
Peak memory 205216 kb
Host smart-357e5a88-75ff-4115-9a98-1101ff8db472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777276088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2777276088
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3153906575
Short name T914
Test name
Test status
Simulation time 114586608 ps
CPU time 2.41 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:55:04 PM PDT 24
Peak memory 221164 kb
Host smart-156b2f85-2e0d-489b-9d9b-149fa61db597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153906575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3153906575
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.4054390837
Short name T628
Test name
Test status
Simulation time 18770685 ps
CPU time 0.82 seconds
Started May 19 01:54:37 PM PDT 24
Finished May 19 01:54:39 PM PDT 24
Peak memory 206804 kb
Host smart-b74db3e8-ff83-4a3f-8392-e873c9d38276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054390837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4054390837
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.267754737
Short name T825
Test name
Test status
Simulation time 12043898134 ps
CPU time 128.45 seconds
Started May 19 01:54:46 PM PDT 24
Finished May 19 01:56:57 PM PDT 24
Peak memory 252680 kb
Host smart-ccc5d8be-7312-4d6a-9b22-e4864dbfe395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267754737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.267754737
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2135585706
Short name T614
Test name
Test status
Simulation time 89708390177 ps
CPU time 302.47 seconds
Started May 19 01:54:45 PM PDT 24
Finished May 19 01:59:50 PM PDT 24
Peak memory 257092 kb
Host smart-cdefb845-9e10-4e90-b58f-52f68c1b03b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135585706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2135585706
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.661061090
Short name T938
Test name
Test status
Simulation time 308707187 ps
CPU time 3.73 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:54:59 PM PDT 24
Peak memory 224572 kb
Host smart-bc9ddb9c-0878-4acd-b7a3-f2159ecfcbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661061090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.661061090
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1501599331
Short name T318
Test name
Test status
Simulation time 264271016 ps
CPU time 3.64 seconds
Started May 19 01:55:00 PM PDT 24
Finished May 19 01:55:10 PM PDT 24
Peak memory 224424 kb
Host smart-9b6213e9-cbb1-42cf-b6fe-14909bce595d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501599331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1501599331
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2009218048
Short name T580
Test name
Test status
Simulation time 17522103502 ps
CPU time 69.01 seconds
Started May 19 01:54:57 PM PDT 24
Finished May 19 01:56:13 PM PDT 24
Peak memory 235932 kb
Host smart-0e59e47e-a8d4-4e7a-aaa4-5cf91d998ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009218048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2009218048
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3725487998
Short name T397
Test name
Test status
Simulation time 148894005 ps
CPU time 1.06 seconds
Started May 19 01:55:00 PM PDT 24
Finished May 19 01:55:07 PM PDT 24
Peak memory 216688 kb
Host smart-abd811b0-8530-4b02-bf42-53812926822b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725487998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3725487998
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3593303935
Short name T238
Test name
Test status
Simulation time 2570505874 ps
CPU time 5.45 seconds
Started May 19 01:54:51 PM PDT 24
Finished May 19 01:55:03 PM PDT 24
Peak memory 218380 kb
Host smart-6d7f2ae0-4803-4ed0-9832-036c35a385c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593303935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3593303935
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1633292042
Short name T240
Test name
Test status
Simulation time 4678066521 ps
CPU time 14.52 seconds
Started May 19 01:54:55 PM PDT 24
Finished May 19 01:55:17 PM PDT 24
Peak memory 229180 kb
Host smart-a387500c-4852-4299-9f99-5b582a0e197e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633292042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1633292042
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.429700341
Short name T12
Test name
Test status
Simulation time 465253672 ps
CPU time 4.57 seconds
Started May 19 01:54:51 PM PDT 24
Finished May 19 01:55:03 PM PDT 24
Peak memory 220624 kb
Host smart-d4bd5650-b182-4551-b4fb-9f77839326af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=429700341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.429700341
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3666866496
Short name T252
Test name
Test status
Simulation time 33803712231 ps
CPU time 232.08 seconds
Started May 19 01:55:00 PM PDT 24
Finished May 19 01:58:58 PM PDT 24
Peak memory 257560 kb
Host smart-2772340a-d9eb-4200-93cc-71e65a4ef880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666866496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3666866496
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.213738536
Short name T715
Test name
Test status
Simulation time 938189666 ps
CPU time 3.07 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:04 PM PDT 24
Peak memory 216328 kb
Host smart-7ba150f9-6453-4772-8928-dcfe7c16e9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213738536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.213738536
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3580963526
Short name T855
Test name
Test status
Simulation time 2606914524 ps
CPU time 7.7 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:55:01 PM PDT 24
Peak memory 216508 kb
Host smart-311d8cf6-783e-418a-ac84-21f4e6f1dea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580963526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3580963526
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2410911966
Short name T930
Test name
Test status
Simulation time 133184968 ps
CPU time 1.86 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:03 PM PDT 24
Peak memory 216396 kb
Host smart-e01cddde-6aed-4201-a048-8359ebf89434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410911966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2410911966
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3471856737
Short name T749
Test name
Test status
Simulation time 163469899 ps
CPU time 0.72 seconds
Started May 19 01:55:03 PM PDT 24
Finished May 19 01:55:08 PM PDT 24
Peak memory 205864 kb
Host smart-a171cd66-5fc5-4f2d-88c3-738d5dafd342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471856737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3471856737
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.485042533
Short name T883
Test name
Test status
Simulation time 118700584 ps
CPU time 2.13 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:54:58 PM PDT 24
Peak memory 207996 kb
Host smart-3aa9a39c-5ace-4b70-b81a-4aa656f69a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485042533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.485042533
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.431033724
Short name T549
Test name
Test status
Simulation time 45630017 ps
CPU time 0.77 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:02 PM PDT 24
Peak memory 205676 kb
Host smart-be8d90f4-a4af-4999-914a-2b48858ebe93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431033724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.431033724
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1352022387
Short name T775
Test name
Test status
Simulation time 36991716 ps
CPU time 2.37 seconds
Started May 19 01:54:56 PM PDT 24
Finished May 19 01:55:06 PM PDT 24
Peak memory 234252 kb
Host smart-326aed74-b9a0-4de8-a931-95cf3b7130da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352022387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1352022387
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.123915175
Short name T506
Test name
Test status
Simulation time 36804265 ps
CPU time 0.74 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:54:55 PM PDT 24
Peak memory 206728 kb
Host smart-42050041-5cdf-4408-8a04-a5655249e875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123915175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.123915175
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.971838458
Short name T289
Test name
Test status
Simulation time 3007119643 ps
CPU time 54.85 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:55:50 PM PDT 24
Peak memory 249248 kb
Host smart-9505c2f0-fe16-4873-94a9-2e924a17c9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971838458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.971838458
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1371451660
Short name T273
Test name
Test status
Simulation time 6055458519 ps
CPU time 140.34 seconds
Started May 19 01:54:45 PM PDT 24
Finished May 19 01:57:09 PM PDT 24
Peak memory 272548 kb
Host smart-c05d871f-05a6-4029-874e-963e8ae916f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371451660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1371451660
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.4242696600
Short name T360
Test name
Test status
Simulation time 143795954148 ps
CPU time 370.23 seconds
Started May 19 01:55:01 PM PDT 24
Finished May 19 02:01:17 PM PDT 24
Peak memory 263184 kb
Host smart-e750acd5-ac57-4855-88a4-aaa98013f8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242696600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.4242696600
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1924532282
Short name T457
Test name
Test status
Simulation time 188479925 ps
CPU time 4.81 seconds
Started May 19 01:54:58 PM PDT 24
Finished May 19 01:55:10 PM PDT 24
Peak memory 232732 kb
Host smart-5ebbf352-e7d5-4a1d-8592-be127b1c4955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924532282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1924532282
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.4189689331
Short name T378
Test name
Test status
Simulation time 200082994 ps
CPU time 2.89 seconds
Started May 19 01:54:50 PM PDT 24
Finished May 19 01:54:59 PM PDT 24
Peak memory 235320 kb
Host smart-4d21d45d-de1a-4daf-9151-938f1e7e688a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189689331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.4189689331
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.573916104
Short name T527
Test name
Test status
Simulation time 84420838369 ps
CPU time 90.24 seconds
Started May 19 01:55:02 PM PDT 24
Finished May 19 01:56:37 PM PDT 24
Peak memory 237708 kb
Host smart-b5a0a508-7127-49f1-be23-2f6104d69ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573916104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.573916104
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.766642492
Short name T27
Test name
Test status
Simulation time 16886224 ps
CPU time 1.08 seconds
Started May 19 01:55:17 PM PDT 24
Finished May 19 01:55:20 PM PDT 24
Peak memory 216712 kb
Host smart-230356d1-1f54-4551-916a-dc9d2d0ca07b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766642492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.766642492
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.704740832
Short name T474
Test name
Test status
Simulation time 4013547024 ps
CPU time 13.91 seconds
Started May 19 01:54:46 PM PDT 24
Finished May 19 01:55:04 PM PDT 24
Peak memory 234500 kb
Host smart-c66913a0-3b40-4bfc-9de9-bb40b381d966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704740832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.704740832
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3101244482
Short name T687
Test name
Test status
Simulation time 3590550564 ps
CPU time 6.51 seconds
Started May 19 01:54:58 PM PDT 24
Finished May 19 01:55:12 PM PDT 24
Peak memory 235112 kb
Host smart-8ef092a5-46fd-4bff-9a5c-d4fb3f829cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101244482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3101244482
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.962038793
Short name T11
Test name
Test status
Simulation time 479006378 ps
CPU time 8.81 seconds
Started May 19 01:54:47 PM PDT 24
Finished May 19 01:54:59 PM PDT 24
Peak memory 220240 kb
Host smart-b02984a6-9e0f-44ac-b883-8b19292e8de8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=962038793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.962038793
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1958964440
Short name T623
Test name
Test status
Simulation time 669074043940 ps
CPU time 339.06 seconds
Started May 19 01:54:48 PM PDT 24
Finished May 19 02:00:31 PM PDT 24
Peak memory 253484 kb
Host smart-ed9492ad-4d08-4bfe-a9d0-5b9812f5510e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958964440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1958964440
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2029798805
Short name T359
Test name
Test status
Simulation time 1346641163 ps
CPU time 14.08 seconds
Started May 19 01:54:51 PM PDT 24
Finished May 19 01:55:18 PM PDT 24
Peak memory 216448 kb
Host smart-36212cac-1bec-44a8-bd8e-0fb9fef2c302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029798805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2029798805
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2398584407
Short name T558
Test name
Test status
Simulation time 825237907 ps
CPU time 2.7 seconds
Started May 19 01:54:57 PM PDT 24
Finished May 19 01:55:07 PM PDT 24
Peak memory 216340 kb
Host smart-6d5aef17-e77d-459c-9b95-3e7d48d84063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398584407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2398584407
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1147289152
Short name T790
Test name
Test status
Simulation time 426117899 ps
CPU time 1.07 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:54:57 PM PDT 24
Peak memory 216156 kb
Host smart-1ec80ce4-a52a-4793-8676-217b02b1ac02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147289152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1147289152
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3483071309
Short name T629
Test name
Test status
Simulation time 244981136 ps
CPU time 0.96 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:54:56 PM PDT 24
Peak memory 205712 kb
Host smart-c88555da-a41b-4938-b062-05015c7741df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483071309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3483071309
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1075155461
Short name T766
Test name
Test status
Simulation time 41096166555 ps
CPU time 18.83 seconds
Started May 19 01:55:00 PM PDT 24
Finished May 19 01:55:27 PM PDT 24
Peak memory 219048 kb
Host smart-d3b18c34-a096-4933-a8bf-4fb1da3e3592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075155461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1075155461
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3135128781
Short name T836
Test name
Test status
Simulation time 39322494 ps
CPU time 0.7 seconds
Started May 19 01:54:57 PM PDT 24
Finished May 19 01:55:06 PM PDT 24
Peak memory 204748 kb
Host smart-db5d2b2f-71f7-46d0-814a-cbaf68143f45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135128781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3135128781
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.4163671750
Short name T369
Test name
Test status
Simulation time 31307090 ps
CPU time 0.8 seconds
Started May 19 01:54:55 PM PDT 24
Finished May 19 01:55:03 PM PDT 24
Peak memory 206444 kb
Host smart-2c26457b-1a93-4234-a3c6-e1b3bf58e29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163671750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4163671750
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.707334406
Short name T636
Test name
Test status
Simulation time 3411606065 ps
CPU time 43.5 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:43 PM PDT 24
Peak memory 250752 kb
Host smart-dfeafe05-65f5-4c91-904f-3481471093b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707334406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.707334406
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2563647758
Short name T485
Test name
Test status
Simulation time 259731822961 ps
CPU time 325.05 seconds
Started May 19 01:55:04 PM PDT 24
Finished May 19 02:00:33 PM PDT 24
Peak memory 249580 kb
Host smart-fcb1e872-622e-4fe8-915f-64e6ac038469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563647758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2563647758
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1316089539
Short name T278
Test name
Test status
Simulation time 24361663623 ps
CPU time 236.88 seconds
Started May 19 01:54:51 PM PDT 24
Finished May 19 01:58:55 PM PDT 24
Peak memory 250388 kb
Host smart-ea950981-f615-4030-9f21-e01f8107bb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316089539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1316089539
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.674498666
Short name T634
Test name
Test status
Simulation time 2697477804 ps
CPU time 8.17 seconds
Started May 19 01:54:57 PM PDT 24
Finished May 19 01:55:16 PM PDT 24
Peak memory 236544 kb
Host smart-240ba1c6-9614-456a-9926-612e11d0f9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674498666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.674498666
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1994313635
Short name T613
Test name
Test status
Simulation time 143055839 ps
CPU time 3.48 seconds
Started May 19 01:55:07 PM PDT 24
Finished May 19 01:55:13 PM PDT 24
Peak memory 219060 kb
Host smart-88231c50-c14c-4972-827e-252c122970fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994313635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1994313635
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1256865378
Short name T761
Test name
Test status
Simulation time 533376050 ps
CPU time 8.25 seconds
Started May 19 01:54:54 PM PDT 24
Finished May 19 01:55:10 PM PDT 24
Peak memory 224396 kb
Host smart-ae9493b3-2c8d-48b0-9568-c2b18e53be85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256865378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1256865378
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.830641822
Short name T480
Test name
Test status
Simulation time 106415819 ps
CPU time 0.99 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:54:57 PM PDT 24
Peak memory 217968 kb
Host smart-3d521866-8f5a-45cc-9e6c-b645a0415f01
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830641822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.830641822
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.652344009
Short name T314
Test name
Test status
Simulation time 36956676417 ps
CPU time 21.11 seconds
Started May 19 01:54:50 PM PDT 24
Finished May 19 01:55:17 PM PDT 24
Peak memory 218844 kb
Host smart-25c8ab56-9255-457a-9f47-789d7447c36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652344009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.652344009
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3323610017
Short name T328
Test name
Test status
Simulation time 725512377 ps
CPU time 5.29 seconds
Started May 19 01:54:46 PM PDT 24
Finished May 19 01:54:54 PM PDT 24
Peak memory 233176 kb
Host smart-a13a7c10-0d51-4e69-bed1-50b87c4362c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323610017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3323610017
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1154283198
Short name T674
Test name
Test status
Simulation time 476221012 ps
CPU time 6.54 seconds
Started May 19 01:54:54 PM PDT 24
Finished May 19 01:55:09 PM PDT 24
Peak memory 220060 kb
Host smart-b53f5795-aa96-4219-9b44-cdcea6f6c368
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1154283198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1154283198
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1667674929
Short name T166
Test name
Test status
Simulation time 43758987339 ps
CPU time 160.26 seconds
Started May 19 01:54:57 PM PDT 24
Finished May 19 01:57:45 PM PDT 24
Peak memory 249324 kb
Host smart-a6762f88-0428-4a12-b025-54ef704dd2bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667674929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1667674929
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2202160112
Short name T615
Test name
Test status
Simulation time 3050534653 ps
CPU time 17.55 seconds
Started May 19 01:54:50 PM PDT 24
Finished May 19 01:55:14 PM PDT 24
Peak memory 216444 kb
Host smart-3a735680-f45e-46c9-82be-c90fdfb47f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202160112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2202160112
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2738204678
Short name T765
Test name
Test status
Simulation time 6961491347 ps
CPU time 16.86 seconds
Started May 19 01:54:50 PM PDT 24
Finished May 19 01:55:14 PM PDT 24
Peak memory 216496 kb
Host smart-c13e4c94-98d0-4d76-9ade-b26ad8ee7685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738204678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2738204678
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.466436578
Short name T6
Test name
Test status
Simulation time 268010845 ps
CPU time 1.6 seconds
Started May 19 01:55:14 PM PDT 24
Finished May 19 01:55:16 PM PDT 24
Peak memory 216296 kb
Host smart-f05ce760-7638-4bcd-9c83-b6be54995ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466436578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.466436578
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3132597415
Short name T518
Test name
Test status
Simulation time 64985510 ps
CPU time 0.92 seconds
Started May 19 01:54:46 PM PDT 24
Finished May 19 01:54:51 PM PDT 24
Peak memory 205792 kb
Host smart-472fc1ff-a51d-4f94-b4a4-07f48bdfe644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132597415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3132597415
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.992068924
Short name T412
Test name
Test status
Simulation time 416604409 ps
CPU time 2.23 seconds
Started May 19 01:55:06 PM PDT 24
Finished May 19 01:55:12 PM PDT 24
Peak memory 208120 kb
Host smart-aaa309f4-2a1a-4aec-a905-7be45d288e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992068924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.992068924
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1736154468
Short name T869
Test name
Test status
Simulation time 30731980 ps
CPU time 0.67 seconds
Started May 19 01:54:50 PM PDT 24
Finished May 19 01:54:58 PM PDT 24
Peak memory 204736 kb
Host smart-9b7cbea3-cfcd-428c-9526-398c2d587c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736154468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1736154468
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3247822719
Short name T596
Test name
Test status
Simulation time 224996704 ps
CPU time 2.88 seconds
Started May 19 01:55:11 PM PDT 24
Finished May 19 01:55:15 PM PDT 24
Peak memory 234348 kb
Host smart-2c0e06d2-3151-4a69-b770-1b77cb7384df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247822719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3247822719
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.601076671
Short name T824
Test name
Test status
Simulation time 169534806 ps
CPU time 0.82 seconds
Started May 19 01:55:09 PM PDT 24
Finished May 19 01:55:12 PM PDT 24
Peak memory 206408 kb
Host smart-fbaa27cb-a10c-40be-aaee-af1c879f7619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601076671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.601076671
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1073438613
Short name T248
Test name
Test status
Simulation time 2807616093 ps
CPU time 68.85 seconds
Started May 19 01:55:09 PM PDT 24
Finished May 19 01:56:20 PM PDT 24
Peak memory 250820 kb
Host smart-0eeb0bcc-5415-439f-8db0-fcbc2541b27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073438613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1073438613
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1216624525
Short name T809
Test name
Test status
Simulation time 1438349903 ps
CPU time 13.21 seconds
Started May 19 01:54:58 PM PDT 24
Finished May 19 01:55:19 PM PDT 24
Peak memory 224576 kb
Host smart-2ec4fa11-2dd7-4cdb-8453-e81fd7cb6e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216624525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1216624525
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3395398492
Short name T560
Test name
Test status
Simulation time 1522531980 ps
CPU time 6.6 seconds
Started May 19 01:54:46 PM PDT 24
Finished May 19 01:54:56 PM PDT 24
Peak memory 234308 kb
Host smart-c659a19c-22f0-4898-8045-101f4ef7bd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395398492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3395398492
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.897834963
Short name T221
Test name
Test status
Simulation time 14833345997 ps
CPU time 16.66 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:55:12 PM PDT 24
Peak memory 234044 kb
Host smart-04da5ae7-1801-49df-aadd-92a2707ba062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897834963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.897834963
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1786686768
Short name T667
Test name
Test status
Simulation time 86208006 ps
CPU time 1.12 seconds
Started May 19 01:55:04 PM PDT 24
Finished May 19 01:55:09 PM PDT 24
Peak memory 216712 kb
Host smart-8e8c3077-b395-4093-a092-b64e19a21d5f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786686768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1786686768
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3746681735
Short name T575
Test name
Test status
Simulation time 4480726786 ps
CPU time 10.86 seconds
Started May 19 01:54:51 PM PDT 24
Finished May 19 01:55:09 PM PDT 24
Peak memory 236544 kb
Host smart-a7f90c8d-7fe6-40ed-ab75-54d51d675a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746681735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3746681735
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.352491347
Short name T209
Test name
Test status
Simulation time 58396897 ps
CPU time 2.8 seconds
Started May 19 01:54:59 PM PDT 24
Finished May 19 01:55:08 PM PDT 24
Peak memory 233644 kb
Host smart-f4757be8-a144-4940-8c22-13ec6ff13d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352491347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.352491347
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.289364877
Short name T858
Test name
Test status
Simulation time 672120472 ps
CPU time 6.22 seconds
Started May 19 01:55:00 PM PDT 24
Finished May 19 01:55:12 PM PDT 24
Peak memory 220220 kb
Host smart-a915f50e-f070-47f0-aa91-d5cf430e84d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=289364877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.289364877
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3473097650
Short name T763
Test name
Test status
Simulation time 1850134877 ps
CPU time 6.54 seconds
Started May 19 01:54:45 PM PDT 24
Finished May 19 01:54:54 PM PDT 24
Peak memory 216460 kb
Host smart-376879e3-ae60-4e5d-8b56-1c15748a21a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473097650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3473097650
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1721973010
Short name T153
Test name
Test status
Simulation time 5417035073 ps
CPU time 11.53 seconds
Started May 19 01:54:48 PM PDT 24
Finished May 19 01:55:04 PM PDT 24
Peak memory 216488 kb
Host smart-242b3426-e735-4463-9326-d3b9cda5815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721973010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1721973010
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.644792805
Short name T899
Test name
Test status
Simulation time 20681538 ps
CPU time 0.71 seconds
Started May 19 01:55:06 PM PDT 24
Finished May 19 01:55:10 PM PDT 24
Peak memory 205460 kb
Host smart-1a30cd17-671e-47fc-a7f7-6131b0381b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644792805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.644792805
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2582295276
Short name T748
Test name
Test status
Simulation time 32017476 ps
CPU time 0.8 seconds
Started May 19 01:55:14 PM PDT 24
Finished May 19 01:55:15 PM PDT 24
Peak memory 205888 kb
Host smart-9d7aac89-df9e-4849-84eb-f8cffe25a794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582295276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2582295276
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1318034095
Short name T643
Test name
Test status
Simulation time 5066813545 ps
CPU time 5.13 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:07 PM PDT 24
Peak memory 234060 kb
Host smart-08c41c02-ea94-48f5-a3a9-d925f1912a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318034095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1318034095
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.758460210
Short name T695
Test name
Test status
Simulation time 41887013 ps
CPU time 0.76 seconds
Started May 19 01:54:56 PM PDT 24
Finished May 19 01:55:04 PM PDT 24
Peak memory 204744 kb
Host smart-ebd54d6d-96c0-4459-bdb3-a5460c0911bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758460210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.758460210
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2097511141
Short name T799
Test name
Test status
Simulation time 188700227 ps
CPU time 3.77 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:54:59 PM PDT 24
Peak memory 233996 kb
Host smart-0cd13014-af0b-4404-9c9b-1a73551e402c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097511141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2097511141
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.4209584852
Short name T668
Test name
Test status
Simulation time 80128641 ps
CPU time 0.73 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:00 PM PDT 24
Peak memory 205396 kb
Host smart-e6146198-189e-43b9-8a4b-271ae53f1b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209584852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.4209584852
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.7584062
Short name T977
Test name
Test status
Simulation time 39261092940 ps
CPU time 70.25 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:56:10 PM PDT 24
Peak memory 253464 kb
Host smart-4e5dea73-4a16-4650-82d1-075c033b3e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7584062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.7584062
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3131611468
Short name T251
Test name
Test status
Simulation time 28006187969 ps
CPU time 106.95 seconds
Started May 19 01:54:54 PM PDT 24
Finished May 19 01:56:49 PM PDT 24
Peak memory 252296 kb
Host smart-115d8afb-0f91-4d13-8d08-d4851bf73040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131611468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3131611468
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3258400169
Short name T915
Test name
Test status
Simulation time 171186789 ps
CPU time 6.64 seconds
Started May 19 01:54:58 PM PDT 24
Finished May 19 01:55:11 PM PDT 24
Peak memory 232752 kb
Host smart-767669d1-792f-4e48-8d23-cbe88300d2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258400169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3258400169
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3123856980
Short name T746
Test name
Test status
Simulation time 605650385 ps
CPU time 3.99 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:55:00 PM PDT 24
Peak memory 234028 kb
Host smart-6d4a890a-0672-45f4-9a48-0213e2b636d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123856980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3123856980
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3156049714
Short name T800
Test name
Test status
Simulation time 247623033 ps
CPU time 4.18 seconds
Started May 19 01:55:01 PM PDT 24
Finished May 19 01:55:11 PM PDT 24
Peak memory 234704 kb
Host smart-d228fee6-7742-4ac0-9d4c-02680b0d66a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156049714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3156049714
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.853147977
Short name T795
Test name
Test status
Simulation time 95236122 ps
CPU time 0.98 seconds
Started May 19 01:54:51 PM PDT 24
Finished May 19 01:55:05 PM PDT 24
Peak memory 217964 kb
Host smart-d2d8e18d-9f74-4a5e-a611-4fa351ede696
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853147977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.853147977
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.967159456
Short name T978
Test name
Test status
Simulation time 3064302675 ps
CPU time 9.7 seconds
Started May 19 01:54:57 PM PDT 24
Finished May 19 01:55:14 PM PDT 24
Peak memory 237796 kb
Host smart-656da4be-ed4d-4110-9c1a-ef3f6ba7b951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967159456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.967159456
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.207182669
Short name T321
Test name
Test status
Simulation time 512167511 ps
CPU time 3.88 seconds
Started May 19 01:54:56 PM PDT 24
Finished May 19 01:55:08 PM PDT 24
Peak memory 233652 kb
Host smart-8e07431c-8679-419c-9fa7-f0152f7df17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207182669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.207182669
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1334620922
Short name T727
Test name
Test status
Simulation time 522183774 ps
CPU time 3.11 seconds
Started May 19 01:54:51 PM PDT 24
Finished May 19 01:55:07 PM PDT 24
Peak memory 220060 kb
Host smart-15f98253-8075-4106-bc2f-08c8d6db9eab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1334620922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1334620922
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3022667058
Short name T68
Test name
Test status
Simulation time 56499900 ps
CPU time 1.02 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:06 PM PDT 24
Peak memory 207088 kb
Host smart-c6b0ab7b-ecda-4e70-bf60-07a9d456ca84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022667058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3022667058
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4092184656
Short name T859
Test name
Test status
Simulation time 34608679298 ps
CPU time 34.42 seconds
Started May 19 01:54:51 PM PDT 24
Finished May 19 01:55:33 PM PDT 24
Peak memory 216748 kb
Host smart-60513b76-ef89-4b5b-89f8-08ec349443e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092184656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4092184656
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.177836659
Short name T682
Test name
Test status
Simulation time 497446033 ps
CPU time 3.68 seconds
Started May 19 01:55:03 PM PDT 24
Finished May 19 01:55:11 PM PDT 24
Peak memory 216300 kb
Host smart-6b239a67-915e-47cd-bef3-895c6f77b542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177836659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.177836659
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3351397566
Short name T8
Test name
Test status
Simulation time 309927687 ps
CPU time 1.95 seconds
Started May 19 01:54:51 PM PDT 24
Finished May 19 01:55:00 PM PDT 24
Peak memory 216348 kb
Host smart-4390dbca-1e77-4781-9f56-c42cd4b46464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351397566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3351397566
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3285607149
Short name T828
Test name
Test status
Simulation time 88209180 ps
CPU time 0.76 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:02 PM PDT 24
Peak memory 205852 kb
Host smart-c20575f0-cd3e-428e-aa6f-ea0d56504526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285607149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3285607149
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1561225459
Short name T335
Test name
Test status
Simulation time 445737140 ps
CPU time 9 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:10 PM PDT 24
Peak memory 250380 kb
Host smart-2fd5c577-5230-4254-9e7a-3593ff4872bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561225459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1561225459
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2802333754
Short name T421
Test name
Test status
Simulation time 22905920 ps
CPU time 0.72 seconds
Started May 19 01:54:55 PM PDT 24
Finished May 19 01:55:04 PM PDT 24
Peak memory 205356 kb
Host smart-42600ba5-0e46-48a4-9627-6f88d43e3bf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802333754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2802333754
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3523825186
Short name T568
Test name
Test status
Simulation time 274995912 ps
CPU time 4.39 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:04 PM PDT 24
Peak memory 217800 kb
Host smart-f1bfdea7-2325-4150-8e0f-c7b5088dc83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523825186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3523825186
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3746216284
Short name T689
Test name
Test status
Simulation time 15235823 ps
CPU time 0.75 seconds
Started May 19 01:54:54 PM PDT 24
Finished May 19 01:55:02 PM PDT 24
Peak memory 206800 kb
Host smart-41af7f39-725f-4821-9bdb-c7c4aa57f6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746216284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3746216284
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2256413450
Short name T870
Test name
Test status
Simulation time 8641437808 ps
CPU time 54.89 seconds
Started May 19 01:54:56 PM PDT 24
Finished May 19 01:55:59 PM PDT 24
Peak memory 249672 kb
Host smart-6a800027-827f-4f83-b3df-dcf0283050a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256413450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2256413450
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1783527292
Short name T358
Test name
Test status
Simulation time 2403321112 ps
CPU time 8.86 seconds
Started May 19 01:54:48 PM PDT 24
Finished May 19 01:55:01 PM PDT 24
Peak memory 217536 kb
Host smart-fd10092c-c608-430c-9dc2-99272c2e3dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783527292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1783527292
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1816368609
Short name T567
Test name
Test status
Simulation time 4331255102 ps
CPU time 36.12 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:36 PM PDT 24
Peak memory 240904 kb
Host smart-de1b87d1-a3f3-4a36-9b48-635b7d3f0a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816368609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1816368609
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3071221199
Short name T889
Test name
Test status
Simulation time 598951760 ps
CPU time 4.69 seconds
Started May 19 01:54:54 PM PDT 24
Finished May 19 01:55:07 PM PDT 24
Peak memory 218732 kb
Host smart-ccce9401-d751-494e-be43-c54787b26335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071221199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3071221199
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2102740279
Short name T640
Test name
Test status
Simulation time 8134992461 ps
CPU time 24.3 seconds
Started May 19 01:55:14 PM PDT 24
Finished May 19 01:55:39 PM PDT 24
Peak memory 220000 kb
Host smart-165b359b-bffd-46dc-b673-93bcb04210ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102740279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2102740279
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1336078195
Short name T526
Test name
Test status
Simulation time 91920313 ps
CPU time 0.98 seconds
Started May 19 01:54:57 PM PDT 24
Finished May 19 01:55:05 PM PDT 24
Peak memory 216728 kb
Host smart-7bfe22de-4486-47a6-8855-a98728859410
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336078195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1336078195
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1420370159
Short name T903
Test name
Test status
Simulation time 20201082705 ps
CPU time 15.15 seconds
Started May 19 01:55:09 PM PDT 24
Finished May 19 01:55:27 PM PDT 24
Peak memory 219716 kb
Host smart-a1e8fc56-ccb8-467d-b0f7-f28610cad019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420370159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1420370159
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1992236201
Short name T305
Test name
Test status
Simulation time 38626550234 ps
CPU time 10.78 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:11 PM PDT 24
Peak memory 218668 kb
Host smart-4acef071-5e50-4b91-b8e9-6bf473cf75f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992236201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1992236201
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2375079771
Short name T399
Test name
Test status
Simulation time 6517068968 ps
CPU time 18.87 seconds
Started May 19 01:55:00 PM PDT 24
Finished May 19 01:55:25 PM PDT 24
Peak memory 219364 kb
Host smart-e15efc54-4739-4e29-be18-d22a979217f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2375079771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2375079771
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3154207121
Short name T931
Test name
Test status
Simulation time 38429670 ps
CPU time 0.92 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:02 PM PDT 24
Peak memory 206828 kb
Host smart-75e44985-629c-440c-a2a5-105faa81a413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154207121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3154207121
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.390650479
Short name T477
Test name
Test status
Simulation time 732601430 ps
CPU time 3.85 seconds
Started May 19 01:55:17 PM PDT 24
Finished May 19 01:55:23 PM PDT 24
Peak memory 216356 kb
Host smart-2742ac23-1cc8-4c0e-b374-f6cdc7be0890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390650479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.390650479
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.4019653713
Short name T417
Test name
Test status
Simulation time 4162433229 ps
CPU time 4.86 seconds
Started May 19 01:55:06 PM PDT 24
Finished May 19 01:55:14 PM PDT 24
Peak memory 216496 kb
Host smart-b7804fee-521b-4797-a7f3-a58f8eb68a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019653713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.4019653713
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.990353281
Short name T361
Test name
Test status
Simulation time 34590348 ps
CPU time 0.83 seconds
Started May 19 01:54:59 PM PDT 24
Finished May 19 01:55:06 PM PDT 24
Peak memory 206676 kb
Host smart-961ddb8d-1bfc-4b8c-b263-75728a0d3751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990353281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.990353281
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1061147861
Short name T374
Test name
Test status
Simulation time 19853778 ps
CPU time 0.77 seconds
Started May 19 01:55:03 PM PDT 24
Finished May 19 01:55:08 PM PDT 24
Peak memory 205836 kb
Host smart-eb4c89cd-c9fb-4671-9937-9698658397e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061147861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1061147861
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2992806973
Short name T511
Test name
Test status
Simulation time 7864674848 ps
CPU time 9.93 seconds
Started May 19 01:54:51 PM PDT 24
Finished May 19 01:55:08 PM PDT 24
Peak memory 220588 kb
Host smart-396d6213-0fdd-4191-81bc-1f65fab1dd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992806973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2992806973
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3503915953
Short name T862
Test name
Test status
Simulation time 12890046 ps
CPU time 0.72 seconds
Started May 19 01:55:11 PM PDT 24
Finished May 19 01:55:13 PM PDT 24
Peak memory 205876 kb
Host smart-350258ce-6a35-4eb2-b86d-69d142db0308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503915953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3503915953
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.926657994
Short name T781
Test name
Test status
Simulation time 138002230 ps
CPU time 3.78 seconds
Started May 19 01:55:13 PM PDT 24
Finished May 19 01:55:18 PM PDT 24
Peak memory 233784 kb
Host smart-50344b2c-22d1-489a-9c5a-59c3f1f38831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926657994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.926657994
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2055033033
Short name T555
Test name
Test status
Simulation time 21628752 ps
CPU time 0.74 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:00 PM PDT 24
Peak memory 205748 kb
Host smart-9971b107-0d7a-465f-8644-d43820d22940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055033033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2055033033
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2378516385
Short name T424
Test name
Test status
Simulation time 66568867 ps
CPU time 0.82 seconds
Started May 19 01:54:50 PM PDT 24
Finished May 19 01:55:06 PM PDT 24
Peak memory 215968 kb
Host smart-ea9d23c0-08a1-4915-b8e4-6135b2e8aa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378516385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2378516385
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1258980388
Short name T797
Test name
Test status
Simulation time 1461915429 ps
CPU time 14.15 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:15 PM PDT 24
Peak memory 217392 kb
Host smart-5327e882-ca9b-46e1-be2d-a8f5e008c799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258980388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1258980388
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2560143919
Short name T228
Test name
Test status
Simulation time 2246910383 ps
CPU time 16.17 seconds
Started May 19 01:54:57 PM PDT 24
Finished May 19 01:55:21 PM PDT 24
Peak memory 250660 kb
Host smart-5c0bf80e-fe77-4b10-a915-fb34b11fc0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560143919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2560143919
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2929600319
Short name T672
Test name
Test status
Simulation time 6361184995 ps
CPU time 27.94 seconds
Started May 19 01:55:03 PM PDT 24
Finished May 19 01:55:35 PM PDT 24
Peak memory 249336 kb
Host smart-a9417719-ac16-4e11-a0c9-a83441529538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929600319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2929600319
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.54119393
Short name T243
Test name
Test status
Simulation time 2122076834 ps
CPU time 13.43 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:12 PM PDT 24
Peak memory 224432 kb
Host smart-ad5fba3f-a300-487e-9625-5652f0753b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54119393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.54119393
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2438800970
Short name T331
Test name
Test status
Simulation time 4518007169 ps
CPU time 12.78 seconds
Started May 19 01:54:55 PM PDT 24
Finished May 19 01:55:16 PM PDT 24
Peak memory 245636 kb
Host smart-07536e00-7295-483a-bf47-17ca895e0b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438800970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2438800970
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3012406942
Short name T559
Test name
Test status
Simulation time 16440466 ps
CPU time 1.03 seconds
Started May 19 01:54:51 PM PDT 24
Finished May 19 01:55:04 PM PDT 24
Peak memory 216688 kb
Host smart-e3f394c0-522b-4acf-a3b4-f767247ae33a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012406942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3012406942
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3122926307
Short name T792
Test name
Test status
Simulation time 38850387 ps
CPU time 2.37 seconds
Started May 19 01:54:54 PM PDT 24
Finished May 19 01:55:04 PM PDT 24
Peak memory 221020 kb
Host smart-c9660418-7e8c-4abf-892d-379a1ba40b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122926307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3122926307
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2836259665
Short name T612
Test name
Test status
Simulation time 34075157822 ps
CPU time 29.27 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:30 PM PDT 24
Peak memory 224604 kb
Host smart-bbe222d0-49b9-4f2a-9f56-8f1fd87cc2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836259665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2836259665
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2977436863
Short name T833
Test name
Test status
Simulation time 415967521 ps
CPU time 4.47 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:06 PM PDT 24
Peak memory 222312 kb
Host smart-24ee8eaa-244d-482c-8eb7-70e4eb5df2e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2977436863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2977436863
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.158929912
Short name T801
Test name
Test status
Simulation time 6381289366 ps
CPU time 9.57 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:09 PM PDT 24
Peak memory 216544 kb
Host smart-9f34faa0-984f-4bc1-bc6e-47ada2dff0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158929912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.158929912
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.519179195
Short name T509
Test name
Test status
Simulation time 5776564321 ps
CPU time 17.35 seconds
Started May 19 01:54:57 PM PDT 24
Finished May 19 01:55:22 PM PDT 24
Peak memory 216512 kb
Host smart-841956a3-f4e5-44cf-a45c-2ee5dd41bc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519179195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.519179195
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1859266601
Short name T5
Test name
Test status
Simulation time 44261853 ps
CPU time 1.17 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:00 PM PDT 24
Peak memory 216304 kb
Host smart-ab1a7b1d-ff98-4543-81fe-abaa6b80f4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859266601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1859266601
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.739400721
Short name T632
Test name
Test status
Simulation time 66849264 ps
CPU time 0.83 seconds
Started May 19 01:54:55 PM PDT 24
Finished May 19 01:55:04 PM PDT 24
Peak memory 205780 kb
Host smart-7d5df87e-fdff-4b63-808d-7870767ade45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739400721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.739400721
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1047811805
Short name T499
Test name
Test status
Simulation time 437028484 ps
CPU time 3.8 seconds
Started May 19 01:54:54 PM PDT 24
Finished May 19 01:55:06 PM PDT 24
Peak memory 234648 kb
Host smart-a2c9dfe0-3057-4a43-84e8-3418e90887f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047811805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1047811805
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2242231091
Short name T656
Test name
Test status
Simulation time 57032713 ps
CPU time 0.76 seconds
Started May 19 01:55:10 PM PDT 24
Finished May 19 01:55:13 PM PDT 24
Peak memory 205356 kb
Host smart-8a447a1b-8959-45cc-8aae-fd6a25adf013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242231091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2242231091
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.937569710
Short name T909
Test name
Test status
Simulation time 77127087 ps
CPU time 2.27 seconds
Started May 19 01:55:09 PM PDT 24
Finished May 19 01:55:13 PM PDT 24
Peak memory 216704 kb
Host smart-258488f7-ca8f-457c-85ed-2fa83d14f0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937569710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.937569710
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3539254522
Short name T890
Test name
Test status
Simulation time 22248304 ps
CPU time 0.74 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:00 PM PDT 24
Peak memory 206464 kb
Host smart-628ffdbf-9043-4f66-a3f3-ce0c51b2da11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539254522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3539254522
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.155983870
Short name T730
Test name
Test status
Simulation time 2087540742 ps
CPU time 21.19 seconds
Started May 19 01:55:19 PM PDT 24
Finished May 19 01:55:42 PM PDT 24
Peak memory 241136 kb
Host smart-82a71458-dceb-4a1f-9388-ae084d778e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155983870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.155983870
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3843932753
Short name T666
Test name
Test status
Simulation time 91062908140 ps
CPU time 99.93 seconds
Started May 19 01:55:19 PM PDT 24
Finished May 19 01:57:01 PM PDT 24
Peak memory 234304 kb
Host smart-967f5550-7610-442b-bcd0-b3380f2b4917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843932753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3843932753
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3687833100
Short name T13
Test name
Test status
Simulation time 1942995483 ps
CPU time 8.58 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:10 PM PDT 24
Peak memory 232740 kb
Host smart-7104ba1b-c793-45c8-9f30-9cdb9e014250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687833100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3687833100
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3415766129
Short name T89
Test name
Test status
Simulation time 4360708062 ps
CPU time 22.86 seconds
Started May 19 01:55:00 PM PDT 24
Finished May 19 01:55:29 PM PDT 24
Peak memory 233588 kb
Host smart-21d67686-f122-4f22-81ff-113a8a2ee6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415766129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3415766129
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3270788555
Short name T336
Test name
Test status
Simulation time 18588704834 ps
CPU time 45.15 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:55:39 PM PDT 24
Peak memory 236872 kb
Host smart-e13697cb-2bda-4ea3-aeb0-c30e5392b656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270788555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3270788555
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3565717674
Short name T371
Test name
Test status
Simulation time 225491997 ps
CPU time 1.03 seconds
Started May 19 01:54:56 PM PDT 24
Finished May 19 01:55:04 PM PDT 24
Peak memory 217996 kb
Host smart-f79d23f9-173c-4bf3-8a6b-4bf3b6743ed4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565717674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3565717674
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.987490587
Short name T429
Test name
Test status
Simulation time 36846835 ps
CPU time 2.34 seconds
Started May 19 01:54:58 PM PDT 24
Finished May 19 01:55:08 PM PDT 24
Peak memory 232684 kb
Host smart-1f852737-bcde-4966-9c8c-43af7fe3cdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987490587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.987490587
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.20643383
Short name T298
Test name
Test status
Simulation time 1152047754 ps
CPU time 8.99 seconds
Started May 19 01:54:46 PM PDT 24
Finished May 19 01:54:58 PM PDT 24
Peak memory 232656 kb
Host smart-92dc90af-3b12-4b73-9dcd-61497289cc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20643383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.20643383
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3462880189
Short name T173
Test name
Test status
Simulation time 5748445788 ps
CPU time 13.74 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:13 PM PDT 24
Peak memory 223068 kb
Host smart-8daff592-2d30-4841-bd60-d3eb7764ea6e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3462880189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3462880189
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1322841177
Short name T807
Test name
Test status
Simulation time 442856849711 ps
CPU time 384.66 seconds
Started May 19 01:55:18 PM PDT 24
Finished May 19 02:01:45 PM PDT 24
Peak memory 256272 kb
Host smart-af85ccf7-a35e-4b42-a3e5-58721f9d66d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322841177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1322841177
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1294440855
Short name T354
Test name
Test status
Simulation time 4901726438 ps
CPU time 13.49 seconds
Started May 19 01:54:56 PM PDT 24
Finished May 19 01:55:18 PM PDT 24
Peak memory 216516 kb
Host smart-ebff3604-3559-4951-b1c2-e80bae94a2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294440855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1294440855
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4094973471
Short name T611
Test name
Test status
Simulation time 3899178773 ps
CPU time 11.87 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:11 PM PDT 24
Peak memory 216484 kb
Host smart-60b58a85-b52a-41ca-a5b3-44c7ee584c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094973471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4094973471
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1158293465
Short name T491
Test name
Test status
Simulation time 1120308085 ps
CPU time 5.65 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:06 PM PDT 24
Peak memory 216472 kb
Host smart-ebcf170f-ee56-40ef-bd55-c8b8ee4627e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158293465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1158293465
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3826971841
Short name T846
Test name
Test status
Simulation time 70954595 ps
CPU time 0.87 seconds
Started May 19 01:55:15 PM PDT 24
Finished May 19 01:55:17 PM PDT 24
Peak memory 206000 kb
Host smart-172e78ed-2b47-4756-9112-c333d127ef75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826971841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3826971841
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3004947327
Short name T786
Test name
Test status
Simulation time 1234336101 ps
CPU time 6.64 seconds
Started May 19 01:55:08 PM PDT 24
Finished May 19 01:55:17 PM PDT 24
Peak memory 227480 kb
Host smart-79457c25-0274-4f25-8805-bb4694df646a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004947327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3004947327
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2894833204
Short name T398
Test name
Test status
Simulation time 46684444 ps
CPU time 0.74 seconds
Started May 19 01:55:16 PM PDT 24
Finished May 19 01:55:19 PM PDT 24
Peak memory 205388 kb
Host smart-d5b535f0-e626-429b-bbd7-94970cb811c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894833204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2894833204
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.503605190
Short name T34
Test name
Test status
Simulation time 71266788 ps
CPU time 2.46 seconds
Started May 19 01:55:06 PM PDT 24
Finished May 19 01:55:11 PM PDT 24
Peak memory 233280 kb
Host smart-1b089ebd-b052-415c-864e-582af201cc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503605190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.503605190
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2036738416
Short name T433
Test name
Test status
Simulation time 19673181 ps
CPU time 0.84 seconds
Started May 19 01:55:13 PM PDT 24
Finished May 19 01:55:15 PM PDT 24
Peak memory 206792 kb
Host smart-26d42b02-d6ec-4b68-bec5-70bd3d0959c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036738416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2036738416
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2591478826
Short name T453
Test name
Test status
Simulation time 6600253661 ps
CPU time 28.32 seconds
Started May 19 01:55:18 PM PDT 24
Finished May 19 01:55:48 PM PDT 24
Peak memory 222780 kb
Host smart-31b156ed-4714-48e9-8cf7-a335b8cfe7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591478826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2591478826
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3928132720
Short name T929
Test name
Test status
Simulation time 2154702646 ps
CPU time 50.8 seconds
Started May 19 01:54:54 PM PDT 24
Finished May 19 01:55:53 PM PDT 24
Peak memory 250716 kb
Host smart-1219c5fa-b0b4-422c-9223-7cecd73f7fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928132720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3928132720
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2510210930
Short name T479
Test name
Test status
Simulation time 726873719 ps
CPU time 13.16 seconds
Started May 19 01:55:19 PM PDT 24
Finished May 19 01:55:34 PM PDT 24
Peak memory 224556 kb
Host smart-e2f43c5c-9ad0-4bda-a463-4158ee4601f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510210930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2510210930
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3310667311
Short name T683
Test name
Test status
Simulation time 220445551 ps
CPU time 4.69 seconds
Started May 19 01:55:18 PM PDT 24
Finished May 19 01:55:25 PM PDT 24
Peak memory 234528 kb
Host smart-3f58744f-9020-4006-a772-8c352cc046b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310667311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3310667311
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3390166534
Short name T303
Test name
Test status
Simulation time 1760029857 ps
CPU time 9.29 seconds
Started May 19 01:54:57 PM PDT 24
Finished May 19 01:55:14 PM PDT 24
Peak memory 232716 kb
Host smart-5e8d96d0-d46d-4914-a4aa-da8b2b91cb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390166534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3390166534
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1397799648
Short name T691
Test name
Test status
Simulation time 122477066 ps
CPU time 0.96 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:00 PM PDT 24
Peak memory 217988 kb
Host smart-027c7847-1e8f-423b-8ab2-cca16fc6b9fa
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397799648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1397799648
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1786981060
Short name T205
Test name
Test status
Simulation time 367620012 ps
CPU time 3.59 seconds
Started May 19 01:55:08 PM PDT 24
Finished May 19 01:55:14 PM PDT 24
Peak memory 218396 kb
Host smart-04571db2-9712-4ccd-bb8a-874f654c4650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786981060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1786981060
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.122642894
Short name T330
Test name
Test status
Simulation time 1195433820 ps
CPU time 4.62 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:05 PM PDT 24
Peak memory 218884 kb
Host smart-b7441839-e915-4f97-8148-549f8fafce02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122642894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.122642894
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.259235926
Short name T940
Test name
Test status
Simulation time 133916245 ps
CPU time 3.55 seconds
Started May 19 01:55:06 PM PDT 24
Finished May 19 01:55:13 PM PDT 24
Peak memory 221872 kb
Host smart-644297c2-021d-4603-8839-d50d0937caba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=259235926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.259235926
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3054168685
Short name T541
Test name
Test status
Simulation time 8531565393 ps
CPU time 27.1 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:28 PM PDT 24
Peak memory 220196 kb
Host smart-9690bc4d-c20f-441e-aabf-d4eccb0da56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054168685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3054168685
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2297458063
Short name T941
Test name
Test status
Simulation time 22904771 ps
CPU time 0.77 seconds
Started May 19 01:55:07 PM PDT 24
Finished May 19 01:55:11 PM PDT 24
Peak memory 205540 kb
Host smart-b6d90481-f8bc-4630-8cbd-326286ad7e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297458063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2297458063
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1686764596
Short name T448
Test name
Test status
Simulation time 98207046 ps
CPU time 4.18 seconds
Started May 19 01:54:51 PM PDT 24
Finished May 19 01:55:02 PM PDT 24
Peak memory 216388 kb
Host smart-ec941599-2050-4bd0-9954-dac5aa5b635a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686764596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1686764596
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2883112018
Short name T386
Test name
Test status
Simulation time 51964807 ps
CPU time 0.8 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:01 PM PDT 24
Peak memory 205832 kb
Host smart-6afd4747-9b07-43e1-a656-d87ca8a00a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883112018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2883112018
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1089605065
Short name T933
Test name
Test status
Simulation time 601536273 ps
CPU time 4.21 seconds
Started May 19 01:55:13 PM PDT 24
Finished May 19 01:55:17 PM PDT 24
Peak memory 234412 kb
Host smart-9fe846fa-1e5a-4386-a8dc-8e332e614eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089605065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1089605065
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3270958641
Short name T922
Test name
Test status
Simulation time 24863821 ps
CPU time 0.76 seconds
Started May 19 01:55:13 PM PDT 24
Finished May 19 01:55:15 PM PDT 24
Peak memory 205360 kb
Host smart-fa21c15a-f398-4755-aef9-b40d3cd75957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270958641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3270958641
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2036791716
Short name T334
Test name
Test status
Simulation time 194677929 ps
CPU time 2.94 seconds
Started May 19 01:55:02 PM PDT 24
Finished May 19 01:55:10 PM PDT 24
Peak memory 234364 kb
Host smart-fb7be392-ee52-4411-858f-afc82463d1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036791716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2036791716
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.4076259732
Short name T69
Test name
Test status
Simulation time 44785725 ps
CPU time 0.72 seconds
Started May 19 01:55:07 PM PDT 24
Finished May 19 01:55:10 PM PDT 24
Peak memory 205308 kb
Host smart-48ab7e8d-0e7d-4378-beb0-de68cf1216ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076259732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4076259732
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.4051677059
Short name T918
Test name
Test status
Simulation time 3964889132 ps
CPU time 10.37 seconds
Started May 19 01:55:17 PM PDT 24
Finished May 19 01:55:29 PM PDT 24
Peak memory 232896 kb
Host smart-1102e9b0-a7d7-414d-b706-653ae6402a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051677059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.4051677059
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1782035942
Short name T570
Test name
Test status
Simulation time 10683840831 ps
CPU time 63.9 seconds
Started May 19 01:55:20 PM PDT 24
Finished May 19 01:56:26 PM PDT 24
Peak memory 249380 kb
Host smart-3110e917-5bf4-4901-9c06-cc8371f6baba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782035942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1782035942
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3614565311
Short name T80
Test name
Test status
Simulation time 1706273397 ps
CPU time 8.45 seconds
Started May 19 01:55:17 PM PDT 24
Finished May 19 01:55:27 PM PDT 24
Peak memory 240800 kb
Host smart-35e4ed59-d4ed-41f8-bb9b-55d799065cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614565311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3614565311
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3856790445
Short name T912
Test name
Test status
Simulation time 5629613907 ps
CPU time 8.78 seconds
Started May 19 01:54:54 PM PDT 24
Finished May 19 01:55:11 PM PDT 24
Peak memory 234100 kb
Host smart-1d83cce1-c8ba-457d-bd3d-34a688d1ad25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856790445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3856790445
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3699674774
Short name T384
Test name
Test status
Simulation time 458688103 ps
CPU time 2.25 seconds
Started May 19 01:55:02 PM PDT 24
Finished May 19 01:55:09 PM PDT 24
Peak memory 218500 kb
Host smart-2d2da9e3-f076-45ca-8df4-b959925a4c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699674774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3699674774
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2844952770
Short name T724
Test name
Test status
Simulation time 54327517 ps
CPU time 1.04 seconds
Started May 19 01:55:08 PM PDT 24
Finished May 19 01:55:11 PM PDT 24
Peak memory 216728 kb
Host smart-387a91b1-4ba7-4802-bb17-bc7fe1c61f6c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844952770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2844952770
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2042095732
Short name T422
Test name
Test status
Simulation time 3535372651 ps
CPU time 5.31 seconds
Started May 19 01:55:08 PM PDT 24
Finished May 19 01:55:16 PM PDT 24
Peak memory 237060 kb
Host smart-9530175f-f09e-471e-936b-57aeff2925cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042095732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2042095732
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.35292204
Short name T902
Test name
Test status
Simulation time 48551250932 ps
CPU time 29.06 seconds
Started May 19 01:55:16 PM PDT 24
Finished May 19 01:55:47 PM PDT 24
Peak memory 232828 kb
Host smart-d7c79540-6a8f-4455-9ccc-d89bc62ddba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35292204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.35292204
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2973828201
Short name T461
Test name
Test status
Simulation time 222292896 ps
CPU time 3.91 seconds
Started May 19 01:55:17 PM PDT 24
Finished May 19 01:55:24 PM PDT 24
Peak memory 222516 kb
Host smart-c44b46a3-05d3-44f6-90c9-cb72f0bcf8fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2973828201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2973828201
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.149269109
Short name T847
Test name
Test status
Simulation time 1734255332 ps
CPU time 26.26 seconds
Started May 19 01:55:17 PM PDT 24
Finished May 19 01:55:45 PM PDT 24
Peak memory 216532 kb
Host smart-99ce744c-ee3c-4c8b-870d-e8ea5600f582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149269109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.149269109
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2529547333
Short name T426
Test name
Test status
Simulation time 2995664328 ps
CPU time 2.79 seconds
Started May 19 01:55:18 PM PDT 24
Finished May 19 01:55:23 PM PDT 24
Peak memory 216484 kb
Host smart-33a3ab86-2d10-46b5-9e7b-8c7add68470b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529547333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2529547333
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2145447732
Short name T504
Test name
Test status
Simulation time 69433160 ps
CPU time 2.94 seconds
Started May 19 01:55:15 PM PDT 24
Finished May 19 01:55:19 PM PDT 24
Peak memory 216392 kb
Host smart-fddaa203-1dd7-4b39-9aff-ce7d2f7f03c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145447732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2145447732
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.855827509
Short name T655
Test name
Test status
Simulation time 100508048 ps
CPU time 0.97 seconds
Started May 19 01:55:05 PM PDT 24
Finished May 19 01:55:09 PM PDT 24
Peak memory 205752 kb
Host smart-07b8c53a-1553-4b1c-ad3b-13bf3580b691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855827509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.855827509
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1037088541
Short name T211
Test name
Test status
Simulation time 508172691 ps
CPU time 2.69 seconds
Started May 19 01:55:01 PM PDT 24
Finished May 19 01:55:09 PM PDT 24
Peak memory 218768 kb
Host smart-a952d919-ccfd-46d3-9d40-76807fe08a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037088541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1037088541
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1220957781
Short name T390
Test name
Test status
Simulation time 22619468 ps
CPU time 0.74 seconds
Started May 19 01:54:40 PM PDT 24
Finished May 19 01:54:41 PM PDT 24
Peak memory 205696 kb
Host smart-6ca493ac-01db-4b5a-8f53-84e798b86ace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220957781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
220957781
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1617276692
Short name T739
Test name
Test status
Simulation time 331972707 ps
CPU time 6.27 seconds
Started May 19 01:54:31 PM PDT 24
Finished May 19 01:54:38 PM PDT 24
Peak memory 233848 kb
Host smart-1bad2805-ce9a-4cfc-bd73-c77e35fbc2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617276692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1617276692
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1083578449
Short name T587
Test name
Test status
Simulation time 18598531 ps
CPU time 0.74 seconds
Started May 19 01:54:47 PM PDT 24
Finished May 19 01:54:51 PM PDT 24
Peak memory 205732 kb
Host smart-b0c3c2ff-cbfa-4e2a-90ba-532d41312cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083578449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1083578449
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3918041197
Short name T403
Test name
Test status
Simulation time 11084004 ps
CPU time 0.79 seconds
Started May 19 01:54:41 PM PDT 24
Finished May 19 01:54:43 PM PDT 24
Peak memory 215964 kb
Host smart-c2274e48-6e7b-4114-88ea-764fcf0e62e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918041197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3918041197
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.632671720
Short name T942
Test name
Test status
Simulation time 8432640409 ps
CPU time 36.31 seconds
Started May 19 01:54:34 PM PDT 24
Finished May 19 01:55:11 PM PDT 24
Peak memory 249284 kb
Host smart-16ffeb24-51b9-474c-8d1f-b583c264120f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632671720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.632671720
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3918966151
Short name T285
Test name
Test status
Simulation time 8065314821 ps
CPU time 48.41 seconds
Started May 19 01:54:33 PM PDT 24
Finished May 19 01:55:22 PM PDT 24
Peak memory 233000 kb
Host smart-4ea4be88-2add-4b1b-b2ee-fb90ec2e5c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918966151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3918966151
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2634243234
Short name T350
Test name
Test status
Simulation time 4361014937 ps
CPU time 16.28 seconds
Started May 19 01:54:41 PM PDT 24
Finished May 19 01:54:58 PM PDT 24
Peak memory 224716 kb
Host smart-fa0ccf97-5fb3-4172-bd6f-f013f85cb53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634243234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2634243234
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2829398307
Short name T200
Test name
Test status
Simulation time 239665541 ps
CPU time 3.5 seconds
Started May 19 01:54:51 PM PDT 24
Finished May 19 01:55:01 PM PDT 24
Peak memory 218548 kb
Host smart-761a6770-7912-4fdb-81cf-13711f31adb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829398307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2829398307
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1009828654
Short name T502
Test name
Test status
Simulation time 234835506 ps
CPU time 4.62 seconds
Started May 19 01:54:25 PM PDT 24
Finished May 19 01:54:30 PM PDT 24
Peak memory 218660 kb
Host smart-147ab8ca-b786-4872-9e4c-c299877507cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009828654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1009828654
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2730177922
Short name T26
Test name
Test status
Simulation time 47803844 ps
CPU time 1.05 seconds
Started May 19 01:54:45 PM PDT 24
Finished May 19 01:54:48 PM PDT 24
Peak memory 216776 kb
Host smart-e0a0bb8f-6b04-4ba1-9c6f-670da6ce7415
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730177922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2730177922
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3283668928
Short name T44
Test name
Test status
Simulation time 391306383 ps
CPU time 6.32 seconds
Started May 19 01:54:41 PM PDT 24
Finished May 19 01:54:48 PM PDT 24
Peak memory 219040 kb
Host smart-b78f931b-a8d0-4ffe-946c-f7cf6d571f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283668928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3283668928
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2254733825
Short name T969
Test name
Test status
Simulation time 959647918 ps
CPU time 4.94 seconds
Started May 19 01:54:33 PM PDT 24
Finished May 19 01:54:38 PM PDT 24
Peak memory 233324 kb
Host smart-2076f863-e179-43a0-88f1-b6de8a432c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254733825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2254733825
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.663853754
Short name T670
Test name
Test status
Simulation time 4652240871 ps
CPU time 13.15 seconds
Started May 19 01:54:24 PM PDT 24
Finished May 19 01:54:38 PM PDT 24
Peak memory 223100 kb
Host smart-aa99a8bf-20e1-4b76-9648-69c32e1f68e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=663853754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.663853754
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2358884099
Short name T75
Test name
Test status
Simulation time 635657166 ps
CPU time 1.06 seconds
Started May 19 01:54:43 PM PDT 24
Finished May 19 01:54:46 PM PDT 24
Peak memory 235212 kb
Host smart-6b864ed1-e76c-40b3-b145-ae880c643e35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358884099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2358884099
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2480356086
Short name T56
Test name
Test status
Simulation time 178017829882 ps
CPU time 422.11 seconds
Started May 19 01:54:42 PM PDT 24
Finished May 19 02:01:45 PM PDT 24
Peak memory 265780 kb
Host smart-f3754e5d-47a9-4ee3-829c-0b704f2bfeea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480356086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2480356086
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3715767336
Short name T714
Test name
Test status
Simulation time 12024006132 ps
CPU time 17.25 seconds
Started May 19 01:54:37 PM PDT 24
Finished May 19 01:54:55 PM PDT 24
Peak memory 216572 kb
Host smart-035d5f36-4b68-48d8-98e8-233a70ff17a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715767336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3715767336
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2157951989
Short name T696
Test name
Test status
Simulation time 2915717714 ps
CPU time 6.55 seconds
Started May 19 01:54:50 PM PDT 24
Finished May 19 01:55:03 PM PDT 24
Peak memory 216436 kb
Host smart-8119ca65-5a25-42ad-a53e-a526e80fbb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157951989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2157951989
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3202491778
Short name T22
Test name
Test status
Simulation time 30634967 ps
CPU time 0.77 seconds
Started May 19 01:54:33 PM PDT 24
Finished May 19 01:54:35 PM PDT 24
Peak memory 206096 kb
Host smart-6ebf575d-b6c9-4bae-8b32-e0b959cdbe39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202491778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3202491778
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2284756662
Short name T582
Test name
Test status
Simulation time 22778531 ps
CPU time 0.81 seconds
Started May 19 01:54:35 PM PDT 24
Finished May 19 01:54:38 PM PDT 24
Peak memory 205868 kb
Host smart-f6ee9fad-e207-4568-a4ce-133935a46a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284756662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2284756662
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1336809776
Short name T245
Test name
Test status
Simulation time 1975649590 ps
CPU time 8.73 seconds
Started May 19 01:54:37 PM PDT 24
Finished May 19 01:54:47 PM PDT 24
Peak memory 232952 kb
Host smart-da55fc75-b237-4afb-ad9b-b83e39d8dd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336809776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1336809776
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3760675
Short name T517
Test name
Test status
Simulation time 14526132 ps
CPU time 0.71 seconds
Started May 19 01:54:54 PM PDT 24
Finished May 19 01:55:03 PM PDT 24
Peak memory 205420 kb
Host smart-e0c4267b-deff-458b-bfd9-59ea0a01f8e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.3760675
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.4156384980
Short name T722
Test name
Test status
Simulation time 54042521 ps
CPU time 2.35 seconds
Started May 19 01:55:28 PM PDT 24
Finished May 19 01:55:32 PM PDT 24
Peak memory 221604 kb
Host smart-39315933-1572-4f8c-81e2-c2b2ea8f2c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156384980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4156384980
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2970692734
Short name T911
Test name
Test status
Simulation time 76501258 ps
CPU time 0.88 seconds
Started May 19 01:55:16 PM PDT 24
Finished May 19 01:55:19 PM PDT 24
Peak memory 206604 kb
Host smart-8112fcf1-dac3-4dd5-8632-0f650f884015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970692734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2970692734
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.4248583508
Short name T197
Test name
Test status
Simulation time 2236727064 ps
CPU time 51.4 seconds
Started May 19 01:55:20 PM PDT 24
Finished May 19 01:56:13 PM PDT 24
Peak memory 256256 kb
Host smart-695f571f-f3b5-448d-bb45-e2d06ad7dd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248583508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.4248583508
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1442425745
Short name T82
Test name
Test status
Simulation time 10853501243 ps
CPU time 18.82 seconds
Started May 19 01:55:03 PM PDT 24
Finished May 19 01:55:26 PM PDT 24
Peak memory 219476 kb
Host smart-4952d849-ebda-4b94-ac54-3b2da552c5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442425745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1442425745
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2959018550
Short name T427
Test name
Test status
Simulation time 142140962 ps
CPU time 2.22 seconds
Started May 19 01:55:09 PM PDT 24
Finished May 19 01:55:14 PM PDT 24
Peak memory 224532 kb
Host smart-bd18ba6a-b4ef-46a2-87eb-5aacf54235f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959018550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2959018550
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3851273044
Short name T306
Test name
Test status
Simulation time 1758784253 ps
CPU time 17.63 seconds
Started May 19 01:55:01 PM PDT 24
Finished May 19 01:55:24 PM PDT 24
Peak memory 234428 kb
Host smart-e382d597-9dc3-4263-850d-32fff0eefec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851273044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3851273044
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1586084016
Short name T342
Test name
Test status
Simulation time 28373289420 ps
CPU time 42.07 seconds
Started May 19 01:55:10 PM PDT 24
Finished May 19 01:55:54 PM PDT 24
Peak memory 239252 kb
Host smart-b005b9c8-b0e4-4a64-8448-9d6db1827759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586084016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1586084016
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2073249881
Short name T673
Test name
Test status
Simulation time 1983047557 ps
CPU time 7.59 seconds
Started May 19 01:55:10 PM PDT 24
Finished May 19 01:55:19 PM PDT 24
Peak memory 217404 kb
Host smart-31a8afdd-e89a-499a-ae62-aed3101fac7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073249881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2073249881
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.275979184
Short name T703
Test name
Test status
Simulation time 622790431 ps
CPU time 4.68 seconds
Started May 19 01:54:58 PM PDT 24
Finished May 19 01:55:10 PM PDT 24
Peak memory 233124 kb
Host smart-33474ed5-02ab-4503-9640-95c682ad5463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275979184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.275979184
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3205415080
Short name T494
Test name
Test status
Simulation time 5925190148 ps
CPU time 12.99 seconds
Started May 19 01:55:20 PM PDT 24
Finished May 19 01:55:34 PM PDT 24
Peak memory 219920 kb
Host smart-de50236a-2ef8-4cae-996f-7e6faa837abe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3205415080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3205415080
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1068722131
Short name T199
Test name
Test status
Simulation time 86518013086 ps
CPU time 244.94 seconds
Started May 19 01:55:19 PM PDT 24
Finished May 19 01:59:26 PM PDT 24
Peak memory 251420 kb
Host smart-d2402ea3-a7bb-47b7-8542-2f4f7138b44a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068722131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1068722131
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2896769638
Short name T609
Test name
Test status
Simulation time 3345411277 ps
CPU time 18.7 seconds
Started May 19 01:54:58 PM PDT 24
Finished May 19 01:55:24 PM PDT 24
Peak memory 216476 kb
Host smart-57cdea59-464f-45c4-bfc8-34790f230d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896769638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2896769638
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2988589332
Short name T658
Test name
Test status
Simulation time 2164996309 ps
CPU time 11.1 seconds
Started May 19 01:55:13 PM PDT 24
Finished May 19 01:55:25 PM PDT 24
Peak memory 216480 kb
Host smart-f00d6fff-fdfb-4082-aa4b-6c7a93afbb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988589332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2988589332
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3217023691
Short name T410
Test name
Test status
Simulation time 92506022 ps
CPU time 4.31 seconds
Started May 19 01:55:20 PM PDT 24
Finished May 19 01:55:26 PM PDT 24
Peak memory 216416 kb
Host smart-3b95f63b-8d7a-4b25-838e-ba72bf00a0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217023691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3217023691
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.571524685
Short name T861
Test name
Test status
Simulation time 26925946 ps
CPU time 0.8 seconds
Started May 19 01:55:02 PM PDT 24
Finished May 19 01:55:08 PM PDT 24
Peak memory 205812 kb
Host smart-90679d13-bb72-4360-b252-55b40a4fc635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571524685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.571524685
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3725692238
Short name T734
Test name
Test status
Simulation time 110099765 ps
CPU time 2.48 seconds
Started May 19 01:55:02 PM PDT 24
Finished May 19 01:55:09 PM PDT 24
Peak memory 219128 kb
Host smart-1f0bd1ba-90b6-475e-bce2-0299721577fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725692238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3725692238
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2825564763
Short name T586
Test name
Test status
Simulation time 19312287 ps
CPU time 0.68 seconds
Started May 19 01:55:06 PM PDT 24
Finished May 19 01:55:10 PM PDT 24
Peak memory 205388 kb
Host smart-a3274a6f-ea21-420a-b641-5e28f7a511b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825564763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2825564763
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1127539692
Short name T152
Test name
Test status
Simulation time 134984863 ps
CPU time 2.3 seconds
Started May 19 01:55:02 PM PDT 24
Finished May 19 01:55:09 PM PDT 24
Peak memory 218680 kb
Host smart-c42a3b5d-ccfc-4555-83a2-901673f3a3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127539692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1127539692
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2253805364
Short name T65
Test name
Test status
Simulation time 37084736 ps
CPU time 0.8 seconds
Started May 19 01:55:02 PM PDT 24
Finished May 19 01:55:08 PM PDT 24
Peak memory 206456 kb
Host smart-30c3cf60-f888-4b81-af6f-b03b241b33fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253805364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2253805364
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3592701110
Short name T481
Test name
Test status
Simulation time 33373165237 ps
CPU time 66.29 seconds
Started May 19 01:55:07 PM PDT 24
Finished May 19 01:56:16 PM PDT 24
Peak memory 224724 kb
Host smart-24455699-7025-48ad-92d6-f1341df3f6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592701110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3592701110
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.233102625
Short name T190
Test name
Test status
Simulation time 2848018540 ps
CPU time 14.34 seconds
Started May 19 01:55:13 PM PDT 24
Finished May 19 01:55:28 PM PDT 24
Peak memory 223672 kb
Host smart-228cc7f0-c874-4f31-aa56-d14154375d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233102625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.233102625
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3232783393
Short name T892
Test name
Test status
Simulation time 45380015 ps
CPU time 2.54 seconds
Started May 19 01:55:17 PM PDT 24
Finished May 19 01:55:22 PM PDT 24
Peak memory 233004 kb
Host smart-e1cc4c98-3b08-493e-a8a6-67a431551c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232783393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3232783393
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2127183575
Short name T329
Test name
Test status
Simulation time 2771749416 ps
CPU time 26.34 seconds
Started May 19 01:54:59 PM PDT 24
Finished May 19 01:55:32 PM PDT 24
Peak memory 233976 kb
Host smart-84e76095-8dfd-46f9-ac9f-9a02c798232f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127183575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2127183575
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1274229780
Short name T160
Test name
Test status
Simulation time 104477515354 ps
CPU time 57.04 seconds
Started May 19 01:55:16 PM PDT 24
Finished May 19 01:56:15 PM PDT 24
Peak memory 230008 kb
Host smart-f37ea276-0808-4034-984f-b8a75fa65de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274229780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1274229780
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2157513220
Short name T751
Test name
Test status
Simulation time 2493468269 ps
CPU time 4.01 seconds
Started May 19 01:55:16 PM PDT 24
Finished May 19 01:55:23 PM PDT 24
Peak memory 236004 kb
Host smart-ddda86ab-d153-466f-9efc-45ad6e472129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157513220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2157513220
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1652168362
Short name T214
Test name
Test status
Simulation time 3234166765 ps
CPU time 11.85 seconds
Started May 19 01:55:30 PM PDT 24
Finished May 19 01:55:43 PM PDT 24
Peak memory 224632 kb
Host smart-4080866e-e196-4ede-aac8-763352f409f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652168362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1652168362
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2536350402
Short name T877
Test name
Test status
Simulation time 5627882742 ps
CPU time 15.68 seconds
Started May 19 01:55:22 PM PDT 24
Finished May 19 01:55:38 PM PDT 24
Peak memory 219252 kb
Host smart-537976f0-bb7e-4bfd-862a-70f33dcc8301
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2536350402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2536350402
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2933655654
Short name T24
Test name
Test status
Simulation time 253525994175 ps
CPU time 524.37 seconds
Started May 19 01:55:15 PM PDT 24
Finished May 19 02:04:00 PM PDT 24
Peak memory 253012 kb
Host smart-2cd4b6a8-c74b-4cad-847b-eb79c3e403b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933655654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2933655654
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.4131503604
Short name T973
Test name
Test status
Simulation time 1869100446 ps
CPU time 13.38 seconds
Started May 19 01:55:02 PM PDT 24
Finished May 19 01:55:21 PM PDT 24
Peak memory 216348 kb
Host smart-ee648469-6a88-4fe8-8557-998562a9e41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131503604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.4131503604
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3175172213
Short name T486
Test name
Test status
Simulation time 2005741796 ps
CPU time 4.43 seconds
Started May 19 01:55:20 PM PDT 24
Finished May 19 01:55:26 PM PDT 24
Peak memory 216308 kb
Host smart-a9101a70-4902-4a1e-a612-e040cb213cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175172213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3175172213
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2352247921
Short name T840
Test name
Test status
Simulation time 264774738 ps
CPU time 3.13 seconds
Started May 19 01:55:10 PM PDT 24
Finished May 19 01:55:15 PM PDT 24
Peak memory 216556 kb
Host smart-2c3b7a4e-8eb7-4d45-9c50-0780a8815e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352247921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2352247921
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2092490606
Short name T631
Test name
Test status
Simulation time 386470515 ps
CPU time 1 seconds
Started May 19 01:55:06 PM PDT 24
Finished May 19 01:55:10 PM PDT 24
Peak memory 205808 kb
Host smart-c520aef9-6c7f-4372-a83e-d5dd1be76173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092490606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2092490606
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1764162707
Short name T710
Test name
Test status
Simulation time 47308027778 ps
CPU time 14.53 seconds
Started May 19 01:55:10 PM PDT 24
Finished May 19 01:55:26 PM PDT 24
Peak memory 241024 kb
Host smart-f672051d-efdd-475b-8163-ae3d777c757d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764162707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1764162707
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3843614829
Short name T860
Test name
Test status
Simulation time 34727361 ps
CPU time 0.7 seconds
Started May 19 01:55:15 PM PDT 24
Finished May 19 01:55:17 PM PDT 24
Peak memory 204988 kb
Host smart-6a372c04-7bde-4ce7-ae30-f84976371f9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843614829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3843614829
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1507971723
Short name T233
Test name
Test status
Simulation time 920667719 ps
CPU time 3.94 seconds
Started May 19 01:55:25 PM PDT 24
Finished May 19 01:55:30 PM PDT 24
Peak memory 220248 kb
Host smart-2a99bc3b-5791-44f1-8b4d-ff0ca78b652c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507971723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1507971723
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1096094233
Short name T438
Test name
Test status
Simulation time 20996992 ps
CPU time 0.82 seconds
Started May 19 01:55:15 PM PDT 24
Finished May 19 01:55:17 PM PDT 24
Peak memory 205436 kb
Host smart-32fe4c4a-7951-4340-93a8-9379c7d83f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096094233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1096094233
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.397479741
Short name T39
Test name
Test status
Simulation time 31378878858 ps
CPU time 118.08 seconds
Started May 19 01:55:08 PM PDT 24
Finished May 19 01:57:09 PM PDT 24
Peak memory 238412 kb
Host smart-4f85cb33-9526-4bcc-b029-59cdf8cae85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397479741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.397479741
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1577583628
Short name T250
Test name
Test status
Simulation time 5309340341 ps
CPU time 43.99 seconds
Started May 19 01:55:08 PM PDT 24
Finished May 19 01:55:54 PM PDT 24
Peak memory 232884 kb
Host smart-df9a3e6c-736b-4a68-a0b7-9a994ad9c66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577583628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1577583628
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.830590171
Short name T817
Test name
Test status
Simulation time 4823758649 ps
CPU time 67.01 seconds
Started May 19 01:55:23 PM PDT 24
Finished May 19 01:56:31 PM PDT 24
Peak memory 241916 kb
Host smart-9728af4e-c8d3-4456-b777-2bffa307f723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830590171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.830590171
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2818734715
Short name T962
Test name
Test status
Simulation time 173565944 ps
CPU time 7.03 seconds
Started May 19 01:55:18 PM PDT 24
Finished May 19 01:55:27 PM PDT 24
Peak memory 238672 kb
Host smart-974d7ae3-a85f-4db4-b25c-9887f432365c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818734715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2818734715
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3332118302
Short name T202
Test name
Test status
Simulation time 1654532767 ps
CPU time 7.06 seconds
Started May 19 01:55:17 PM PDT 24
Finished May 19 01:55:26 PM PDT 24
Peak memory 217580 kb
Host smart-18c3354c-a584-42eb-9af4-cf8ace9a8cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332118302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3332118302
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3887916978
Short name T300
Test name
Test status
Simulation time 5512271608 ps
CPU time 51.68 seconds
Started May 19 01:55:23 PM PDT 24
Finished May 19 01:56:16 PM PDT 24
Peak memory 233932 kb
Host smart-3bad57ef-cf13-4ed8-8f93-45ae00b6a94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887916978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3887916978
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.4045584314
Short name T844
Test name
Test status
Simulation time 2509021540 ps
CPU time 12.05 seconds
Started May 19 01:55:09 PM PDT 24
Finished May 19 01:55:24 PM PDT 24
Peak memory 230096 kb
Host smart-5473e292-4b34-4f4a-894b-4dc4c08a68c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045584314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.4045584314
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2017043139
Short name T468
Test name
Test status
Simulation time 16582292968 ps
CPU time 11.87 seconds
Started May 19 01:55:09 PM PDT 24
Finished May 19 01:55:24 PM PDT 24
Peak memory 222712 kb
Host smart-a7cccad1-1266-467e-83d3-1aa452994630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017043139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2017043139
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1252997840
Short name T425
Test name
Test status
Simulation time 5717015606 ps
CPU time 10.44 seconds
Started May 19 01:55:16 PM PDT 24
Finished May 19 01:55:29 PM PDT 24
Peak memory 223164 kb
Host smart-77319156-3310-4e88-ab53-0093cdc28b50
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1252997840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1252997840
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2007201906
Short name T815
Test name
Test status
Simulation time 1089279783 ps
CPU time 11.04 seconds
Started May 19 01:55:13 PM PDT 24
Finished May 19 01:55:25 PM PDT 24
Peak memory 216380 kb
Host smart-795b4ae5-0b78-4793-9ccc-683d31ae1038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007201906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2007201906
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3720898860
Short name T811
Test name
Test status
Simulation time 2560028384 ps
CPU time 6.08 seconds
Started May 19 01:55:02 PM PDT 24
Finished May 19 01:55:13 PM PDT 24
Peak memory 216760 kb
Host smart-f6e044ea-8d35-41aa-983f-c31520eb9f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720898860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3720898860
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3831477697
Short name T757
Test name
Test status
Simulation time 229991505 ps
CPU time 1.2 seconds
Started May 19 01:54:57 PM PDT 24
Finished May 19 01:55:08 PM PDT 24
Peak memory 207796 kb
Host smart-ac055f94-07a3-485e-bd77-c2266a6aa087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831477697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3831477697
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1842627759
Short name T415
Test name
Test status
Simulation time 36119943 ps
CPU time 0.72 seconds
Started May 19 01:55:16 PM PDT 24
Finished May 19 01:55:19 PM PDT 24
Peak memory 205824 kb
Host smart-a84aa218-1f67-4e7b-95dc-c04af6bc9b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842627759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1842627759
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2679283893
Short name T385
Test name
Test status
Simulation time 119949903 ps
CPU time 2.35 seconds
Started May 19 01:55:24 PM PDT 24
Finished May 19 01:55:27 PM PDT 24
Peak memory 216312 kb
Host smart-bbef6eab-f22a-432d-89ed-97089a1a56f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679283893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2679283893
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2639832995
Short name T401
Test name
Test status
Simulation time 45026381 ps
CPU time 0.76 seconds
Started May 19 01:55:21 PM PDT 24
Finished May 19 01:55:23 PM PDT 24
Peak memory 204704 kb
Host smart-8b4ffcfd-d5ea-4361-9404-f559f63b9267
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639832995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2639832995
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.599259133
Short name T35
Test name
Test status
Simulation time 505597772 ps
CPU time 4.96 seconds
Started May 19 01:55:15 PM PDT 24
Finished May 19 01:55:21 PM PDT 24
Peak memory 234120 kb
Host smart-7a7c6d6f-1e0d-4243-9a7a-a762f23b456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599259133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.599259133
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.503159115
Short name T523
Test name
Test status
Simulation time 28205132 ps
CPU time 0.81 seconds
Started May 19 01:55:15 PM PDT 24
Finished May 19 01:55:17 PM PDT 24
Peak memory 206452 kb
Host smart-bd96cce1-f621-4f20-aa58-02358de99fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503159115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.503159115
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.891468674
Short name T916
Test name
Test status
Simulation time 26609820429 ps
CPU time 53.7 seconds
Started May 19 01:55:15 PM PDT 24
Finished May 19 01:56:10 PM PDT 24
Peak memory 249264 kb
Host smart-10c83c06-3308-413a-a173-57cdd51edc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891468674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.891468674
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3096597899
Short name T308
Test name
Test status
Simulation time 16941255567 ps
CPU time 46.57 seconds
Started May 19 01:55:28 PM PDT 24
Finished May 19 01:56:15 PM PDT 24
Peak memory 232828 kb
Host smart-1be41a5f-f6b0-4ef9-83b4-b11ec90af7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096597899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3096597899
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.15637366
Short name T21
Test name
Test status
Simulation time 4361330534 ps
CPU time 46.18 seconds
Started May 19 01:55:09 PM PDT 24
Finished May 19 01:55:58 PM PDT 24
Peak memory 250584 kb
Host smart-923dc446-1846-4f9a-b7d4-9854c91c7faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15637366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.15637366
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1367415810
Short name T654
Test name
Test status
Simulation time 1449177189 ps
CPU time 30.94 seconds
Started May 19 01:55:12 PM PDT 24
Finished May 19 01:55:44 PM PDT 24
Peak memory 232716 kb
Host smart-df2f9972-e57d-429a-beb5-8b8681adf36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367415810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1367415810
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1388125967
Short name T980
Test name
Test status
Simulation time 67358515 ps
CPU time 2.48 seconds
Started May 19 01:55:20 PM PDT 24
Finished May 19 01:55:24 PM PDT 24
Peak memory 218728 kb
Host smart-9ceebb87-05a3-4824-a593-90beef7642ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388125967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1388125967
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.897502967
Short name T455
Test name
Test status
Simulation time 118558347 ps
CPU time 2.46 seconds
Started May 19 01:55:13 PM PDT 24
Finished May 19 01:55:17 PM PDT 24
Peak memory 221304 kb
Host smart-27aa0a2f-6db0-415c-a9d5-f6a0f412ede3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897502967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.897502967
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1218598331
Short name T66
Test name
Test status
Simulation time 31890472352 ps
CPU time 22.15 seconds
Started May 19 01:55:30 PM PDT 24
Finished May 19 01:55:53 PM PDT 24
Peak memory 233464 kb
Host smart-2ef905f0-32da-4a75-bd3a-c429c797c0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218598331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1218598331
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2692797700
Short name T648
Test name
Test status
Simulation time 289916370 ps
CPU time 5.71 seconds
Started May 19 01:55:07 PM PDT 24
Finished May 19 01:55:15 PM PDT 24
Peak memory 238536 kb
Host smart-33d1c87f-96d4-4799-ab14-a4aab2d85a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692797700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2692797700
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.528482360
Short name T872
Test name
Test status
Simulation time 995792825 ps
CPU time 8.27 seconds
Started May 19 01:55:15 PM PDT 24
Finished May 19 01:55:24 PM PDT 24
Peak memory 222436 kb
Host smart-2acd576c-b41e-4416-8ca0-8b8661781d03
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=528482360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.528482360
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1512796317
Short name T462
Test name
Test status
Simulation time 20775660030 ps
CPU time 37.26 seconds
Started May 19 01:55:18 PM PDT 24
Finished May 19 01:55:57 PM PDT 24
Peak memory 216356 kb
Host smart-537483fd-cbd0-4754-9fa5-9520c54aef21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512796317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1512796317
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3273713071
Short name T382
Test name
Test status
Simulation time 5436487842 ps
CPU time 7.17 seconds
Started May 19 01:55:18 PM PDT 24
Finished May 19 01:55:27 PM PDT 24
Peak memory 216472 kb
Host smart-c2fed45f-339d-4878-949c-a11f48a3a05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273713071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3273713071
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3595714718
Short name T943
Test name
Test status
Simulation time 19486116 ps
CPU time 1.2 seconds
Started May 19 01:55:18 PM PDT 24
Finished May 19 01:55:22 PM PDT 24
Peak memory 207772 kb
Host smart-727e3d2b-6d1a-4a91-9ef3-61f464d915da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595714718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3595714718
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1092045111
Short name T935
Test name
Test status
Simulation time 79584876 ps
CPU time 0.9 seconds
Started May 19 01:55:18 PM PDT 24
Finished May 19 01:55:21 PM PDT 24
Peak memory 205824 kb
Host smart-ad4c3296-e942-4d5e-b593-cec2ec209e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092045111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1092045111
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.4165936131
Short name T333
Test name
Test status
Simulation time 794762079 ps
CPU time 4.46 seconds
Started May 19 01:55:07 PM PDT 24
Finished May 19 01:55:18 PM PDT 24
Peak memory 218960 kb
Host smart-61b30c67-912c-41d1-afac-ca8898e10cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165936131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.4165936131
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2512065775
Short name T482
Test name
Test status
Simulation time 17699138 ps
CPU time 0.72 seconds
Started May 19 01:55:19 PM PDT 24
Finished May 19 01:55:22 PM PDT 24
Peak memory 204724 kb
Host smart-72a303e8-fc4f-49d4-9e97-ae7cfb7cbe6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512065775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2512065775
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2918381130
Short name T785
Test name
Test status
Simulation time 300210926 ps
CPU time 4.72 seconds
Started May 19 01:55:14 PM PDT 24
Finished May 19 01:55:19 PM PDT 24
Peak memory 219928 kb
Host smart-53be2847-b451-4c3f-89b5-34eb769eeb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918381130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2918381130
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1430952168
Short name T924
Test name
Test status
Simulation time 50204514 ps
CPU time 0.8 seconds
Started May 19 01:55:15 PM PDT 24
Finished May 19 01:55:17 PM PDT 24
Peak memory 206808 kb
Host smart-15cffab2-92ce-4a49-99bd-78f9aa3656cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430952168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1430952168
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2138550972
Short name T721
Test name
Test status
Simulation time 22594440975 ps
CPU time 66.87 seconds
Started May 19 01:55:28 PM PDT 24
Finished May 19 01:56:36 PM PDT 24
Peak memory 240064 kb
Host smart-99efadca-395b-4c53-9e13-fe21a1d77ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138550972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2138550972
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3092795074
Short name T102
Test name
Test status
Simulation time 1895312109 ps
CPU time 30.98 seconds
Started May 19 01:55:21 PM PDT 24
Finished May 19 01:55:53 PM PDT 24
Peak memory 239812 kb
Host smart-66c4b863-e66d-4acd-b625-1df6a1ffe52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092795074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3092795074
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1551259388
Short name T813
Test name
Test status
Simulation time 1850534561 ps
CPU time 6.85 seconds
Started May 19 01:55:20 PM PDT 24
Finished May 19 01:55:28 PM PDT 24
Peak memory 233980 kb
Host smart-3bfa4b03-ed13-450e-b29d-3fde498927fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551259388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1551259388
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3050258969
Short name T653
Test name
Test status
Simulation time 7799343701 ps
CPU time 20.23 seconds
Started May 19 01:55:19 PM PDT 24
Finished May 19 01:55:41 PM PDT 24
Peak memory 218232 kb
Host smart-2c258748-c4ac-4f56-b84c-e88661b3d889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050258969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3050258969
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3535670920
Short name T711
Test name
Test status
Simulation time 9297848283 ps
CPU time 77.61 seconds
Started May 19 01:55:11 PM PDT 24
Finished May 19 01:56:30 PM PDT 24
Peak memory 218628 kb
Host smart-eab02404-c2bd-46e1-8542-5be5b419a40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535670920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3535670920
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.165831018
Short name T157
Test name
Test status
Simulation time 34146263 ps
CPU time 2.47 seconds
Started May 19 01:55:18 PM PDT 24
Finished May 19 01:55:23 PM PDT 24
Peak memory 221160 kb
Host smart-d9b2adeb-b0da-4366-bea5-0b37c49658be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165831018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.165831018
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2613335038
Short name T322
Test name
Test status
Simulation time 234953995 ps
CPU time 2.47 seconds
Started May 19 01:55:25 PM PDT 24
Finished May 19 01:55:28 PM PDT 24
Peak memory 218896 kb
Host smart-698c5688-fcf9-4d11-8b41-42c436bae7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613335038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2613335038
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2492450227
Short name T590
Test name
Test status
Simulation time 218954597 ps
CPU time 4.01 seconds
Started May 19 01:55:16 PM PDT 24
Finished May 19 01:55:21 PM PDT 24
Peak memory 222904 kb
Host smart-caa6952c-45ff-47a6-b8e5-8e1f3c749c07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2492450227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2492450227
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.4171704359
Short name T155
Test name
Test status
Simulation time 43477286616 ps
CPU time 439.35 seconds
Started May 19 01:55:17 PM PDT 24
Finished May 19 02:02:38 PM PDT 24
Peak memory 272676 kb
Host smart-aca10782-3124-4e9b-ba34-f27812636361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171704359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.4171704359
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2363286083
Short name T578
Test name
Test status
Simulation time 17100131282 ps
CPU time 13.88 seconds
Started May 19 01:55:25 PM PDT 24
Finished May 19 01:55:41 PM PDT 24
Peak memory 216564 kb
Host smart-1108c98a-b616-425b-87b1-2726a95aaa3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363286083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2363286083
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1768979600
Short name T705
Test name
Test status
Simulation time 1855971619 ps
CPU time 4.62 seconds
Started May 19 01:55:16 PM PDT 24
Finished May 19 01:55:23 PM PDT 24
Peak memory 216312 kb
Host smart-bbc6871f-8724-4afa-a7e8-1d444653789f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768979600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1768979600
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.4184547321
Short name T515
Test name
Test status
Simulation time 189809264 ps
CPU time 5.59 seconds
Started May 19 01:55:16 PM PDT 24
Finished May 19 01:55:24 PM PDT 24
Peak memory 216356 kb
Host smart-0663ac2f-bfac-4f1d-b9bb-d33e2d74f845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184547321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.4184547321
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.4231212430
Short name T874
Test name
Test status
Simulation time 87889263 ps
CPU time 0.77 seconds
Started May 19 01:55:24 PM PDT 24
Finished May 19 01:55:26 PM PDT 24
Peak memory 205856 kb
Host smart-8497d97a-933c-4186-8dde-8c77d3ac78a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231212430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.4231212430
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3963636799
Short name T236
Test name
Test status
Simulation time 1995326236 ps
CPU time 11.44 seconds
Started May 19 01:55:18 PM PDT 24
Finished May 19 01:55:32 PM PDT 24
Peak memory 256472 kb
Host smart-93ce2d0a-5083-40bd-9701-a79743947ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963636799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3963636799
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3469669028
Short name T366
Test name
Test status
Simulation time 15842348 ps
CPU time 0.7 seconds
Started May 19 01:55:23 PM PDT 24
Finished May 19 01:55:25 PM PDT 24
Peak memory 204692 kb
Host smart-fe77f0aa-0a3e-40cf-8638-c0106111e685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469669028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3469669028
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.749414181
Short name T841
Test name
Test status
Simulation time 626224699 ps
CPU time 9.18 seconds
Started May 19 01:55:37 PM PDT 24
Finished May 19 01:55:47 PM PDT 24
Peak memory 233464 kb
Host smart-d7c1afb7-4de5-448b-8223-f4b4c8896e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749414181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.749414181
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3982647914
Short name T651
Test name
Test status
Simulation time 43124913 ps
CPU time 0.79 seconds
Started May 19 01:55:25 PM PDT 24
Finished May 19 01:55:27 PM PDT 24
Peak memory 206800 kb
Host smart-6087a5cd-2847-40d4-87f5-46b0363c255a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982647914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3982647914
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1020728024
Short name T184
Test name
Test status
Simulation time 65039411394 ps
CPU time 116.06 seconds
Started May 19 01:55:31 PM PDT 24
Finished May 19 01:57:28 PM PDT 24
Peak memory 249264 kb
Host smart-ad88de50-4792-486d-8d64-2a5ff82ac5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020728024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1020728024
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2823189911
Short name T536
Test name
Test status
Simulation time 9660610157 ps
CPU time 13.38 seconds
Started May 19 01:55:25 PM PDT 24
Finished May 19 01:55:40 PM PDT 24
Peak memory 217616 kb
Host smart-68417303-f1ee-4551-a1e3-8cb04d6c1e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823189911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2823189911
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2706973766
Short name T619
Test name
Test status
Simulation time 3970305050 ps
CPU time 19.51 seconds
Started May 19 01:55:18 PM PDT 24
Finished May 19 01:55:40 PM PDT 24
Peak memory 232812 kb
Host smart-b04c554b-ba89-41eb-a780-ff3d3174b6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706973766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2706973766
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3167680816
Short name T708
Test name
Test status
Simulation time 104130319 ps
CPU time 2.37 seconds
Started May 19 01:55:17 PM PDT 24
Finished May 19 01:55:22 PM PDT 24
Peak memory 216200 kb
Host smart-1ceeb22a-93ff-450b-a7eb-1cf236f672c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167680816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3167680816
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4109843057
Short name T45
Test name
Test status
Simulation time 1029494670 ps
CPU time 5.91 seconds
Started May 19 01:55:15 PM PDT 24
Finished May 19 01:55:23 PM PDT 24
Peak memory 218628 kb
Host smart-c52d05eb-8f06-4de0-9120-9ec27450d01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109843057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.4109843057
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.38356406
Short name T48
Test name
Test status
Simulation time 4332089221 ps
CPU time 15.84 seconds
Started May 19 01:55:19 PM PDT 24
Finished May 19 01:55:37 PM PDT 24
Peak memory 217904 kb
Host smart-533a2224-fca1-44a3-9ac4-6d0eba395143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38356406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.38356406
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.4041809878
Short name T707
Test name
Test status
Simulation time 4627124952 ps
CPU time 5.2 seconds
Started May 19 01:55:37 PM PDT 24
Finished May 19 01:55:44 PM PDT 24
Peak memory 218544 kb
Host smart-d84c41bb-f505-4505-bec6-bcc66e3b5e90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4041809878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.4041809878
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1123300990
Short name T98
Test name
Test status
Simulation time 8061353126 ps
CPU time 88.6 seconds
Started May 19 01:55:30 PM PDT 24
Finished May 19 01:57:00 PM PDT 24
Peak memory 248804 kb
Host smart-a3dfa35d-0126-4f76-af8c-6d089ad01942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123300990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1123300990
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1969511768
Short name T30
Test name
Test status
Simulation time 2863800483 ps
CPU time 22.69 seconds
Started May 19 01:55:14 PM PDT 24
Finished May 19 01:55:38 PM PDT 24
Peak memory 216544 kb
Host smart-385f14ab-06c3-4484-ad61-9e906f988042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969511768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1969511768
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.224616562
Short name T442
Test name
Test status
Simulation time 379387479 ps
CPU time 1.33 seconds
Started May 19 01:55:22 PM PDT 24
Finished May 19 01:55:24 PM PDT 24
Peak memory 207772 kb
Host smart-f3e06956-cb9f-4a08-a012-140411df9e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224616562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.224616562
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1582799690
Short name T793
Test name
Test status
Simulation time 53340724 ps
CPU time 0.68 seconds
Started May 19 01:55:25 PM PDT 24
Finished May 19 01:55:27 PM PDT 24
Peak memory 205696 kb
Host smart-0ed1a5d7-58f4-40cb-b18c-510656932885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582799690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1582799690
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.4118187071
Short name T610
Test name
Test status
Simulation time 32794995 ps
CPU time 0.77 seconds
Started May 19 01:55:29 PM PDT 24
Finished May 19 01:55:31 PM PDT 24
Peak memory 205848 kb
Host smart-53e69afe-f62b-43cf-aa52-e9af61bfbf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118187071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.4118187071
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3558023880
Short name T607
Test name
Test status
Simulation time 139217254 ps
CPU time 2.68 seconds
Started May 19 01:55:33 PM PDT 24
Finished May 19 01:55:37 PM PDT 24
Peak memory 232760 kb
Host smart-331c9480-87dd-4e20-adde-2c721073bda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558023880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3558023880
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3583195080
Short name T822
Test name
Test status
Simulation time 102682765 ps
CPU time 0.71 seconds
Started May 19 01:55:36 PM PDT 24
Finished May 19 01:55:37 PM PDT 24
Peak memory 205384 kb
Host smart-adc53c61-aa94-4fb9-8452-31b3076dbea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583195080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3583195080
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2606944807
Short name T681
Test name
Test status
Simulation time 163894354 ps
CPU time 3.69 seconds
Started May 19 01:55:28 PM PDT 24
Finished May 19 01:55:33 PM PDT 24
Peak memory 218440 kb
Host smart-5b551a50-b27c-4e0c-aeef-433861bbeeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606944807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2606944807
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3750720943
Short name T503
Test name
Test status
Simulation time 48827389 ps
CPU time 0.75 seconds
Started May 19 01:55:26 PM PDT 24
Finished May 19 01:55:28 PM PDT 24
Peak memory 206792 kb
Host smart-81af61eb-9a7f-4646-926f-c383f67d37f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750720943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3750720943
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1103916012
Short name T192
Test name
Test status
Simulation time 54271858112 ps
CPU time 99.24 seconds
Started May 19 01:55:19 PM PDT 24
Finished May 19 01:57:00 PM PDT 24
Peak memory 239128 kb
Host smart-c00c5427-aeb2-45d0-a0c1-d532d4109ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103916012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1103916012
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3385998499
Short name T189
Test name
Test status
Simulation time 2577933600 ps
CPU time 57.51 seconds
Started May 19 01:55:36 PM PDT 24
Finished May 19 01:56:34 PM PDT 24
Peak memory 248988 kb
Host smart-930b0550-22e2-4e35-a350-c73ba14e9d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385998499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3385998499
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3530882698
Short name T277
Test name
Test status
Simulation time 8024679962 ps
CPU time 74.87 seconds
Started May 19 01:55:22 PM PDT 24
Finished May 19 01:56:38 PM PDT 24
Peak memory 233052 kb
Host smart-b058c769-c000-41a5-b8de-492d17ac5ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530882698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3530882698
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.224874917
Short name T470
Test name
Test status
Simulation time 121933134 ps
CPU time 3.17 seconds
Started May 19 01:55:26 PM PDT 24
Finished May 19 01:55:30 PM PDT 24
Peak memory 234156 kb
Host smart-669eef11-6208-4467-943d-a9a650c1569a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224874917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.224874917
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2931694998
Short name T641
Test name
Test status
Simulation time 5137989001 ps
CPU time 15.74 seconds
Started May 19 01:55:31 PM PDT 24
Finished May 19 01:55:48 PM PDT 24
Peak memory 235260 kb
Host smart-9e2a3bf8-2a70-4ad8-a3e3-98a375955ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931694998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2931694998
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2827501515
Short name T849
Test name
Test status
Simulation time 1126101327 ps
CPU time 7.06 seconds
Started May 19 01:55:32 PM PDT 24
Finished May 19 01:55:40 PM PDT 24
Peak memory 217812 kb
Host smart-389fc8e9-645c-44aa-aa62-ff39def901f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827501515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2827501515
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1255250510
Short name T966
Test name
Test status
Simulation time 841406469 ps
CPU time 4.79 seconds
Started May 19 01:55:25 PM PDT 24
Finished May 19 01:55:31 PM PDT 24
Peak memory 233736 kb
Host smart-487e00c9-2c38-440f-9829-80ee53134df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255250510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1255250510
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.717176726
Short name T646
Test name
Test status
Simulation time 1180442521 ps
CPU time 9.46 seconds
Started May 19 01:55:25 PM PDT 24
Finished May 19 01:55:36 PM PDT 24
Peak memory 232624 kb
Host smart-78755323-b542-4ec4-b593-ac75b038d0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717176726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.717176726
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.793153946
Short name T671
Test name
Test status
Simulation time 90952661 ps
CPU time 3.34 seconds
Started May 19 01:55:20 PM PDT 24
Finished May 19 01:55:29 PM PDT 24
Peak memory 218816 kb
Host smart-6d0f6872-7ed0-420f-98c2-6429edbfb733
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=793153946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.793153946
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.476137063
Short name T961
Test name
Test status
Simulation time 139058432190 ps
CPU time 674.54 seconds
Started May 19 01:55:30 PM PDT 24
Finished May 19 02:06:46 PM PDT 24
Peak memory 272584 kb
Host smart-ab139f29-5891-46db-9907-907ac76047d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476137063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.476137063
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3878120927
Short name T925
Test name
Test status
Simulation time 868265638 ps
CPU time 11.14 seconds
Started May 19 01:55:42 PM PDT 24
Finished May 19 01:55:54 PM PDT 24
Peak memory 216420 kb
Host smart-1845b94c-906d-4452-ab83-823190c386cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878120927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3878120927
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.118133071
Short name T584
Test name
Test status
Simulation time 6096744607 ps
CPU time 7.88 seconds
Started May 19 01:55:28 PM PDT 24
Finished May 19 01:55:37 PM PDT 24
Peak memory 216536 kb
Host smart-ccf94e2f-d6e5-4992-be3c-76522431301e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118133071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.118133071
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1396901938
Short name T375
Test name
Test status
Simulation time 20762820 ps
CPU time 0.96 seconds
Started May 19 01:55:39 PM PDT 24
Finished May 19 01:55:41 PM PDT 24
Peak memory 206676 kb
Host smart-dc33b67e-c0fb-4c2a-b7c4-86bf155cc14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396901938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1396901938
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2767208370
Short name T886
Test name
Test status
Simulation time 165912381 ps
CPU time 0.96 seconds
Started May 19 01:55:26 PM PDT 24
Finished May 19 01:55:28 PM PDT 24
Peak memory 205836 kb
Host smart-dc277f08-c7d4-48a0-9691-c6d53e597708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767208370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2767208370
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.724069455
Short name T332
Test name
Test status
Simulation time 3469003071 ps
CPU time 7.11 seconds
Started May 19 01:55:36 PM PDT 24
Finished May 19 01:55:44 PM PDT 24
Peak memory 234400 kb
Host smart-0bf0b03e-b073-431a-b7d2-a7068b99b48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724069455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.724069455
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1908348626
Short name T83
Test name
Test status
Simulation time 23815606 ps
CPU time 0.77 seconds
Started May 19 01:55:25 PM PDT 24
Finished May 19 01:55:27 PM PDT 24
Peak memory 205640 kb
Host smart-16afcc7e-4a15-413c-a9f3-e5dc01103892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908348626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1908348626
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.513191884
Short name T581
Test name
Test status
Simulation time 139728612 ps
CPU time 2.78 seconds
Started May 19 01:55:38 PM PDT 24
Finished May 19 01:55:42 PM PDT 24
Peak memory 218728 kb
Host smart-bdf9ccd4-020e-4156-9ae4-5a8e9e38ace7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513191884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.513191884
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2753055459
Short name T444
Test name
Test status
Simulation time 82133700 ps
CPU time 0.78 seconds
Started May 19 01:55:24 PM PDT 24
Finished May 19 01:55:25 PM PDT 24
Peak memory 206796 kb
Host smart-3f1e9cda-71be-40d5-aebf-bf7cf8a8cb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753055459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2753055459
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.725260226
Short name T212
Test name
Test status
Simulation time 113667787592 ps
CPU time 58.31 seconds
Started May 19 01:55:36 PM PDT 24
Finished May 19 01:56:35 PM PDT 24
Peak memory 234568 kb
Host smart-42b084e7-ab81-4b69-9b5d-3702187bec8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725260226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.725260226
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1932920043
Short name T971
Test name
Test status
Simulation time 37401248765 ps
CPU time 115.09 seconds
Started May 19 01:55:30 PM PDT 24
Finished May 19 01:57:26 PM PDT 24
Peak memory 250952 kb
Host smart-b910b515-bbf7-42eb-8977-6e0ee992ec3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932920043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1932920043
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3245784169
Short name T316
Test name
Test status
Simulation time 39180836024 ps
CPU time 187.12 seconds
Started May 19 01:55:26 PM PDT 24
Finished May 19 01:58:35 PM PDT 24
Peak memory 249416 kb
Host smart-07c07993-2e03-4ae3-960b-831afa9ab122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245784169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3245784169
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2724955695
Short name T776
Test name
Test status
Simulation time 12994535332 ps
CPU time 37.94 seconds
Started May 19 01:55:28 PM PDT 24
Finished May 19 01:56:07 PM PDT 24
Peak memory 241028 kb
Host smart-20f06a7e-3197-4928-a8ea-80388ee36dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724955695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2724955695
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1470395778
Short name T680
Test name
Test status
Simulation time 105935517 ps
CPU time 2.3 seconds
Started May 19 01:55:28 PM PDT 24
Finished May 19 01:55:32 PM PDT 24
Peak memory 218460 kb
Host smart-456ee35d-3a9f-424f-8685-2eddf34b2d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470395778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1470395778
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3865222547
Short name T469
Test name
Test status
Simulation time 215531539 ps
CPU time 2.07 seconds
Started May 19 01:55:30 PM PDT 24
Finished May 19 01:55:33 PM PDT 24
Peak memory 216136 kb
Host smart-7c287939-3419-42b3-930b-266a45291255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865222547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3865222547
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2993879573
Short name T405
Test name
Test status
Simulation time 96038041 ps
CPU time 2.02 seconds
Started May 19 01:55:33 PM PDT 24
Finished May 19 01:55:36 PM PDT 24
Peak memory 216172 kb
Host smart-cf6ae630-eae9-444b-a77c-6fcd351ecd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993879573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2993879573
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.220075804
Short name T37
Test name
Test status
Simulation time 2692082051 ps
CPU time 10.45 seconds
Started May 19 01:55:22 PM PDT 24
Finished May 19 01:55:34 PM PDT 24
Peak memory 235852 kb
Host smart-eb2459c3-bb8b-4b99-9340-dc64cc7f5c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220075804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.220075804
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.960056703
Short name T458
Test name
Test status
Simulation time 705433793 ps
CPU time 4.36 seconds
Started May 19 01:55:33 PM PDT 24
Finished May 19 01:55:38 PM PDT 24
Peak memory 223036 kb
Host smart-1820c337-9682-4da6-86c8-9ebe341d72bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=960056703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.960056703
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.4176134405
Short name T867
Test name
Test status
Simulation time 13689222292 ps
CPU time 57.01 seconds
Started May 19 01:55:28 PM PDT 24
Finished May 19 01:56:26 PM PDT 24
Peak memory 249720 kb
Host smart-7d4b938f-aab6-4881-9282-d0d5798c5468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176134405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.4176134405
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1887354860
Short name T665
Test name
Test status
Simulation time 87615896 ps
CPU time 0.73 seconds
Started May 19 01:55:23 PM PDT 24
Finished May 19 01:55:25 PM PDT 24
Peak memory 205548 kb
Host smart-7514d5ff-3e67-4d4e-a3a5-cd2a615a98f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887354860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1887354860
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3312731105
Short name T907
Test name
Test status
Simulation time 1189176582 ps
CPU time 3.26 seconds
Started May 19 01:55:25 PM PDT 24
Finished May 19 01:55:30 PM PDT 24
Peak memory 216352 kb
Host smart-d188ec50-e453-4025-9346-aa18e72b1106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312731105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3312731105
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.212162968
Short name T435
Test name
Test status
Simulation time 237861482 ps
CPU time 2.2 seconds
Started May 19 01:55:30 PM PDT 24
Finished May 19 01:55:33 PM PDT 24
Peak memory 216392 kb
Host smart-6077e6ba-afde-46bc-918d-e8d0fd42e7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212162968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.212162968
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2418038801
Short name T637
Test name
Test status
Simulation time 208415519 ps
CPU time 0.81 seconds
Started May 19 01:55:28 PM PDT 24
Finished May 19 01:55:30 PM PDT 24
Peak memory 205836 kb
Host smart-b3a0bc50-a1ef-48e3-bd5d-5ddf643a5149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418038801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2418038801
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2623375038
Short name T875
Test name
Test status
Simulation time 1855941705 ps
CPU time 10.35 seconds
Started May 19 01:55:36 PM PDT 24
Finished May 19 01:55:47 PM PDT 24
Peak memory 220256 kb
Host smart-6a6c3df1-b380-428d-a148-9a048d36c5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623375038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2623375038
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.4028078545
Short name T500
Test name
Test status
Simulation time 133970899 ps
CPU time 0.71 seconds
Started May 19 01:55:32 PM PDT 24
Finished May 19 01:55:33 PM PDT 24
Peak memory 205408 kb
Host smart-9cf7ea6a-b0e3-4ff2-a4e6-8fa2fff9f3a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028078545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
4028078545
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2924044656
Short name T420
Test name
Test status
Simulation time 146914909 ps
CPU time 2.11 seconds
Started May 19 01:55:27 PM PDT 24
Finished May 19 01:55:30 PM PDT 24
Peak memory 218924 kb
Host smart-99d5df86-9efe-4ea2-876d-b24db7b3a793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924044656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2924044656
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2910346039
Short name T633
Test name
Test status
Simulation time 19460954 ps
CPU time 0.74 seconds
Started May 19 01:55:26 PM PDT 24
Finished May 19 01:55:28 PM PDT 24
Peak memory 205388 kb
Host smart-7b8fa9e4-d37d-45b5-939d-1b6e9cad53a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910346039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2910346039
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1636854908
Short name T188
Test name
Test status
Simulation time 30901171190 ps
CPU time 68.06 seconds
Started May 19 01:55:21 PM PDT 24
Finished May 19 01:56:30 PM PDT 24
Peak memory 252548 kb
Host smart-1d3266f3-d973-4ca5-914b-42730a33e02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636854908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1636854908
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2582780519
Short name T750
Test name
Test status
Simulation time 445454424 ps
CPU time 10.61 seconds
Started May 19 01:55:33 PM PDT 24
Finished May 19 01:55:44 PM PDT 24
Peak memory 224708 kb
Host smart-5c1fbeaa-c2ad-436d-a607-8cbe5e0048b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582780519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2582780519
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2786576496
Short name T839
Test name
Test status
Simulation time 964347174 ps
CPU time 13.93 seconds
Started May 19 01:55:29 PM PDT 24
Finished May 19 01:55:44 PM PDT 24
Peak memory 239216 kb
Host smart-30f8714e-040c-493a-82a2-502f6f15e293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786576496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2786576496
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2875980515
Short name T396
Test name
Test status
Simulation time 28090270 ps
CPU time 2.05 seconds
Started May 19 01:55:25 PM PDT 24
Finished May 19 01:55:29 PM PDT 24
Peak memory 216168 kb
Host smart-793a14d5-eb07-4e63-a19c-b7bf730f7191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875980515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2875980515
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2372826703
Short name T344
Test name
Test status
Simulation time 96888716 ps
CPU time 2.78 seconds
Started May 19 01:55:31 PM PDT 24
Finished May 19 01:55:35 PM PDT 24
Peak memory 234632 kb
Host smart-9cef6b80-8bf3-49b1-9a95-2a7c7f8192b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372826703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2372826703
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.4290006232
Short name T304
Test name
Test status
Simulation time 581945589 ps
CPU time 5.11 seconds
Started May 19 01:55:38 PM PDT 24
Finished May 19 01:55:45 PM PDT 24
Peak memory 233364 kb
Host smart-49f2cf7c-0dae-4c6b-8585-3d8b0d0ba6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290006232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.4290006232
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1395285962
Short name T232
Test name
Test status
Simulation time 1565998316 ps
CPU time 10.84 seconds
Started May 19 01:55:31 PM PDT 24
Finished May 19 01:55:43 PM PDT 24
Peak memory 238856 kb
Host smart-3782b134-563a-4419-b7dc-008e448166d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395285962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1395285962
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3093348763
Short name T413
Test name
Test status
Simulation time 1028849440 ps
CPU time 7.18 seconds
Started May 19 01:55:33 PM PDT 24
Finished May 19 01:55:41 PM PDT 24
Peak memory 220068 kb
Host smart-7e84c20d-1f70-460c-b51e-f3b337eff4b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3093348763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3093348763
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2422873445
Short name T768
Test name
Test status
Simulation time 1341605220 ps
CPU time 20.01 seconds
Started May 19 01:55:27 PM PDT 24
Finished May 19 01:55:48 PM PDT 24
Peak memory 219484 kb
Host smart-76297eb3-5925-466d-a99e-3ae634a5fb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422873445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2422873445
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4057273056
Short name T548
Test name
Test status
Simulation time 98357816 ps
CPU time 1.27 seconds
Started May 19 01:55:38 PM PDT 24
Finished May 19 01:55:40 PM PDT 24
Peak memory 207908 kb
Host smart-d10a30d2-1d67-4516-b675-506ab05ed6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057273056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4057273056
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1534076926
Short name T445
Test name
Test status
Simulation time 62930771 ps
CPU time 0.87 seconds
Started May 19 01:55:30 PM PDT 24
Finished May 19 01:55:32 PM PDT 24
Peak memory 206880 kb
Host smart-df2a1d0a-8b99-4aec-80dc-52d88526a1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534076926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1534076926
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3973598704
Short name T693
Test name
Test status
Simulation time 94916560 ps
CPU time 0.78 seconds
Started May 19 01:55:39 PM PDT 24
Finished May 19 01:55:41 PM PDT 24
Peak memory 205864 kb
Host smart-a290c948-27a6-42a1-92fc-8e9efc53de8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973598704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3973598704
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.201210449
Short name T700
Test name
Test status
Simulation time 30937132649 ps
CPU time 17.17 seconds
Started May 19 01:55:24 PM PDT 24
Finished May 19 01:55:42 PM PDT 24
Peak memory 237904 kb
Host smart-b0f9f912-8141-4f6c-88c2-ea2239dc0f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201210449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.201210449
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1255781308
Short name T968
Test name
Test status
Simulation time 105027646 ps
CPU time 0.72 seconds
Started May 19 01:55:43 PM PDT 24
Finished May 19 01:55:45 PM PDT 24
Peak memory 205668 kb
Host smart-93666089-8a5c-4863-823b-54958f095e01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255781308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1255781308
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2189897445
Short name T459
Test name
Test status
Simulation time 22728361661 ps
CPU time 44.77 seconds
Started May 19 01:55:33 PM PDT 24
Finished May 19 01:56:19 PM PDT 24
Peak memory 221504 kb
Host smart-74ec4ec2-9898-49ae-b4fb-b756af104a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189897445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2189897445
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1354714108
Short name T780
Test name
Test status
Simulation time 15555013 ps
CPU time 0.78 seconds
Started May 19 01:55:38 PM PDT 24
Finished May 19 01:55:40 PM PDT 24
Peak memory 205392 kb
Host smart-33d8b265-1c87-4ae8-8ec5-36995249ccd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354714108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1354714108
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.540778014
Short name T798
Test name
Test status
Simulation time 10856814832 ps
CPU time 53.8 seconds
Started May 19 01:55:41 PM PDT 24
Finished May 19 01:56:35 PM PDT 24
Peak memory 250416 kb
Host smart-573f2b62-9aa0-4749-ac7c-253f3a5cc2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540778014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.540778014
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.106177488
Short name T40
Test name
Test status
Simulation time 7680489996 ps
CPU time 62.71 seconds
Started May 19 01:55:37 PM PDT 24
Finished May 19 01:56:41 PM PDT 24
Peak memory 257532 kb
Host smart-7a2b7478-f2fd-44ee-8321-16817cc4fa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106177488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.106177488
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2921702038
Short name T974
Test name
Test status
Simulation time 1735652014 ps
CPU time 3.92 seconds
Started May 19 01:55:39 PM PDT 24
Finished May 19 01:55:44 PM PDT 24
Peak memory 218724 kb
Host smart-0db78f54-39f2-4c67-8aa8-c5bc1f0067b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921702038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2921702038
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1387855724
Short name T709
Test name
Test status
Simulation time 26290109407 ps
CPU time 88.34 seconds
Started May 19 01:55:41 PM PDT 24
Finished May 19 01:57:10 PM PDT 24
Peak memory 250900 kb
Host smart-59d3ff0b-2bf7-48b6-920c-b84420095f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387855724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1387855724
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1320693580
Short name T664
Test name
Test status
Simulation time 50301960953 ps
CPU time 9 seconds
Started May 19 01:55:32 PM PDT 24
Finished May 19 01:55:42 PM PDT 24
Peak memory 227376 kb
Host smart-bece5776-7734-4c73-95dd-7d10ba351f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320693580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1320693580
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1264846375
Short name T791
Test name
Test status
Simulation time 2230800990 ps
CPU time 9.65 seconds
Started May 19 01:55:39 PM PDT 24
Finished May 19 01:55:49 PM PDT 24
Peak memory 240368 kb
Host smart-10d89e32-f3da-4de1-92c7-aa870d0aa590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264846375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1264846375
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3329092491
Short name T713
Test name
Test status
Simulation time 332403310 ps
CPU time 3.66 seconds
Started May 19 01:55:43 PM PDT 24
Finished May 19 01:55:48 PM PDT 24
Peak memory 218784 kb
Host smart-7c80511d-6f78-441a-84aa-7ee0708abd5e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3329092491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3329092491
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.4033549906
Short name T101
Test name
Test status
Simulation time 22210939776 ps
CPU time 87.41 seconds
Started May 19 01:55:30 PM PDT 24
Finished May 19 01:56:58 PM PDT 24
Peak memory 234504 kb
Host smart-29a9b970-5232-45d2-941c-1e320f91568e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033549906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.4033549906
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2063625551
Short name T357
Test name
Test status
Simulation time 10684860068 ps
CPU time 40.61 seconds
Started May 19 01:55:38 PM PDT 24
Finished May 19 01:56:19 PM PDT 24
Peak memory 216500 kb
Host smart-139a9b74-f7e0-4477-b258-31fd4724c91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063625551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2063625551
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3209226098
Short name T599
Test name
Test status
Simulation time 12924410195 ps
CPU time 9.33 seconds
Started May 19 01:55:35 PM PDT 24
Finished May 19 01:55:45 PM PDT 24
Peak memory 216532 kb
Host smart-7b89fece-a88e-4dc5-aad7-f163a50278aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209226098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3209226098
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3954694955
Short name T948
Test name
Test status
Simulation time 27966081 ps
CPU time 1.28 seconds
Started May 19 01:55:34 PM PDT 24
Finished May 19 01:55:36 PM PDT 24
Peak memory 216280 kb
Host smart-3e6f323a-9101-42c8-a116-51c7a616ac02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954694955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3954694955
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3571259663
Short name T638
Test name
Test status
Simulation time 56030525 ps
CPU time 0.78 seconds
Started May 19 01:55:27 PM PDT 24
Finished May 19 01:55:29 PM PDT 24
Peak memory 205872 kb
Host smart-30537183-38fe-449e-afc0-e4c73f3f9b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571259663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3571259663
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2504517394
Short name T767
Test name
Test status
Simulation time 34980084 ps
CPU time 2.57 seconds
Started May 19 01:55:35 PM PDT 24
Finished May 19 01:55:38 PM PDT 24
Peak memory 212384 kb
Host smart-0a9d8987-b94f-4d4f-8db2-53c5ec5d3265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504517394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2504517394
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1473318117
Short name T475
Test name
Test status
Simulation time 23353025 ps
CPU time 0.74 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:01 PM PDT 24
Peak memory 205404 kb
Host smart-2f5d170a-dd6a-4c02-99cd-7eecff22f6cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473318117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
473318117
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3648556360
Short name T110
Test name
Test status
Simulation time 404813015 ps
CPU time 3.44 seconds
Started May 19 01:54:34 PM PDT 24
Finished May 19 01:54:38 PM PDT 24
Peak memory 218480 kb
Host smart-61c66fd1-d590-4ea9-a2dd-225e02d7ff3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648556360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3648556360
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.809780207
Short name T953
Test name
Test status
Simulation time 15030754 ps
CPU time 0.77 seconds
Started May 19 01:54:32 PM PDT 24
Finished May 19 01:54:33 PM PDT 24
Peak memory 206656 kb
Host smart-c42a9cf8-2149-4981-ba3d-9aad83883e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809780207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.809780207
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2746806999
Short name T756
Test name
Test status
Simulation time 10942361506 ps
CPU time 70.9 seconds
Started May 19 01:54:43 PM PDT 24
Finished May 19 01:55:56 PM PDT 24
Peak memory 249304 kb
Host smart-61a3bd6b-b42e-46fe-ab47-b21413c7140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746806999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2746806999
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1743393795
Short name T262
Test name
Test status
Simulation time 56739997629 ps
CPU time 68.81 seconds
Started May 19 01:54:35 PM PDT 24
Finished May 19 01:55:46 PM PDT 24
Peak memory 251884 kb
Host smart-b496c79d-219b-431c-9203-ec961c353c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743393795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1743393795
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.10840499
Short name T218
Test name
Test status
Simulation time 27386433596 ps
CPU time 66 seconds
Started May 19 01:54:35 PM PDT 24
Finished May 19 01:55:42 PM PDT 24
Peak memory 237316 kb
Host smart-d6b9196e-7f4e-406b-92e5-6704b767f11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10840499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.10840499
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.102995086
Short name T170
Test name
Test status
Simulation time 114065170 ps
CPU time 4.88 seconds
Started May 19 01:54:42 PM PDT 24
Finished May 19 01:54:48 PM PDT 24
Peak memory 232724 kb
Host smart-0bf9d4e4-bf96-407f-8506-d8f935d1e1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102995086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.102995086
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3492648450
Short name T694
Test name
Test status
Simulation time 5147205760 ps
CPU time 16.43 seconds
Started May 19 01:54:31 PM PDT 24
Finished May 19 01:54:48 PM PDT 24
Peak memory 219100 kb
Host smart-4246ffd2-3fec-4a82-8aae-def6e13f3d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492648450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3492648450
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1217874081
Short name T244
Test name
Test status
Simulation time 26973821376 ps
CPU time 68.53 seconds
Started May 19 01:54:47 PM PDT 24
Finished May 19 01:55:59 PM PDT 24
Peak memory 240036 kb
Host smart-b2907cc3-64c3-4e76-9444-cb39e246b4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217874081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1217874081
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3243972615
Short name T25
Test name
Test status
Simulation time 96469633 ps
CPU time 1.04 seconds
Started May 19 01:54:34 PM PDT 24
Finished May 19 01:54:35 PM PDT 24
Peak memory 216764 kb
Host smart-827407f3-deac-41b6-88cb-981dda89c7d0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243972615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3243972615
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3784047696
Short name T388
Test name
Test status
Simulation time 30277374 ps
CPU time 1.97 seconds
Started May 19 01:54:55 PM PDT 24
Finished May 19 01:55:05 PM PDT 24
Peak memory 216216 kb
Host smart-83571283-01f3-48e9-b1a1-0bd53587ac9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784047696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3784047696
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1559941486
Short name T573
Test name
Test status
Simulation time 1215645862 ps
CPU time 3.9 seconds
Started May 19 01:54:40 PM PDT 24
Finished May 19 01:54:45 PM PDT 24
Peak memory 233768 kb
Host smart-ad6a15ed-4045-482f-ac6a-463ab9be7cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559941486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1559941486
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3683414969
Short name T963
Test name
Test status
Simulation time 563574588 ps
CPU time 8.08 seconds
Started May 19 01:54:37 PM PDT 24
Finished May 19 01:54:46 PM PDT 24
Peak memory 218796 kb
Host smart-f338eeb2-8f67-46c5-81ed-6949c5340bfb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3683414969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3683414969
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3795975370
Short name T77
Test name
Test status
Simulation time 164430978 ps
CPU time 1.18 seconds
Started May 19 01:54:42 PM PDT 24
Finished May 19 01:54:44 PM PDT 24
Peak memory 235084 kb
Host smart-bbf4a7d3-ae38-49b6-9b04-67d4aa751bfd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795975370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3795975370
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.311378137
Short name T678
Test name
Test status
Simulation time 36250453 ps
CPU time 0.91 seconds
Started May 19 01:54:39 PM PDT 24
Finished May 19 01:54:41 PM PDT 24
Peak memory 205788 kb
Host smart-6a57ec50-fdbf-4c4f-84bc-57ccb2b042cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311378137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.311378137
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1071217532
Short name T905
Test name
Test status
Simulation time 3397916388 ps
CPU time 27 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:26 PM PDT 24
Peak memory 216532 kb
Host smart-bbb303fa-4fe7-4be7-a68f-ba716add2c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071217532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1071217532
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2864790905
Short name T452
Test name
Test status
Simulation time 8686092881 ps
CPU time 13.36 seconds
Started May 19 01:54:42 PM PDT 24
Finished May 19 01:54:57 PM PDT 24
Peak memory 216544 kb
Host smart-d1478308-5785-41c5-86f1-f21cf0339972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864790905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2864790905
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.571289101
Short name T85
Test name
Test status
Simulation time 171065464 ps
CPU time 2.1 seconds
Started May 19 01:54:43 PM PDT 24
Finished May 19 01:54:47 PM PDT 24
Peak memory 216472 kb
Host smart-2a3b5a3a-fea1-418f-9777-5770bb4b01a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571289101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.571289101
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.536739195
Short name T370
Test name
Test status
Simulation time 25798764 ps
CPU time 0.76 seconds
Started May 19 01:54:34 PM PDT 24
Finished May 19 01:54:35 PM PDT 24
Peak memory 205844 kb
Host smart-7ff0d563-409c-4d52-b4aa-534271325b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536739195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.536739195
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1726519473
Short name T196
Test name
Test status
Simulation time 977200258 ps
CPU time 8.61 seconds
Started May 19 01:54:36 PM PDT 24
Finished May 19 01:54:46 PM PDT 24
Peak memory 223664 kb
Host smart-34525c8e-57ad-4e8f-ba05-e91586a876b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726519473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1726519473
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3977796653
Short name T754
Test name
Test status
Simulation time 24074740 ps
CPU time 0.72 seconds
Started May 19 01:55:31 PM PDT 24
Finished May 19 01:55:32 PM PDT 24
Peak memory 205276 kb
Host smart-f100f0a2-f144-42ba-90de-87bc09bd15f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977796653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3977796653
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.94536375
Short name T593
Test name
Test status
Simulation time 246768063 ps
CPU time 2.07 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:55:57 PM PDT 24
Peak memory 216128 kb
Host smart-8714975c-917c-44ee-add5-36de0837e236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94536375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.94536375
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.112921157
Short name T574
Test name
Test status
Simulation time 157411256 ps
CPU time 0.79 seconds
Started May 19 01:55:37 PM PDT 24
Finished May 19 01:55:39 PM PDT 24
Peak memory 206412 kb
Host smart-3200fe9f-0618-4150-9ac6-40ed743b58e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112921157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.112921157
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3647317797
Short name T488
Test name
Test status
Simulation time 1386594519 ps
CPU time 16.8 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:56:13 PM PDT 24
Peak memory 232624 kb
Host smart-4ddb3d93-8166-4ed0-b848-100c56cbeae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647317797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3647317797
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.85006463
Short name T955
Test name
Test status
Simulation time 12423963939 ps
CPU time 136.81 seconds
Started May 19 01:55:45 PM PDT 24
Finished May 19 01:58:04 PM PDT 24
Peak memory 249384 kb
Host smart-43664e3a-55c2-4ead-b695-d41a6348ec42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85006463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.85006463
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2046462069
Short name T419
Test name
Test status
Simulation time 919092104 ps
CPU time 18.13 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:56:13 PM PDT 24
Peak memory 240880 kb
Host smart-c8c17aa4-461c-4428-9660-aac2cd4be80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046462069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2046462069
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1884078781
Short name T466
Test name
Test status
Simulation time 1172714224 ps
CPU time 20.69 seconds
Started May 19 01:55:45 PM PDT 24
Finished May 19 01:56:10 PM PDT 24
Peak memory 232764 kb
Host smart-22edf5da-a706-42e2-8c66-57c3157d4d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884078781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1884078781
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3211432434
Short name T642
Test name
Test status
Simulation time 273434828 ps
CPU time 5.28 seconds
Started May 19 01:55:41 PM PDT 24
Finished May 19 01:55:48 PM PDT 24
Peak memory 234560 kb
Host smart-9dc0adbd-16a6-4b4a-abec-55c0dba43d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211432434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3211432434
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3238055076
Short name T194
Test name
Test status
Simulation time 317600385 ps
CPU time 11.51 seconds
Started May 19 01:55:38 PM PDT 24
Finished May 19 01:55:51 PM PDT 24
Peak memory 227804 kb
Host smart-75c31f90-e870-43c4-95f1-3d1d10f160df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238055076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3238055076
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.4121709313
Short name T15
Test name
Test status
Simulation time 4216497816 ps
CPU time 8.85 seconds
Started May 19 01:55:41 PM PDT 24
Finished May 19 01:55:51 PM PDT 24
Peak memory 240464 kb
Host smart-f276031d-678c-473f-9c5f-c705e6140c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121709313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.4121709313
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2794640794
Short name T894
Test name
Test status
Simulation time 2717261054 ps
CPU time 6.44 seconds
Started May 19 01:55:34 PM PDT 24
Finished May 19 01:55:41 PM PDT 24
Peak memory 219008 kb
Host smart-46dfe895-f4fd-4394-ab5b-eb540e17e9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794640794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2794640794
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3662916497
Short name T826
Test name
Test status
Simulation time 638807784 ps
CPU time 4.51 seconds
Started May 19 01:55:41 PM PDT 24
Finished May 19 01:55:47 PM PDT 24
Peak memory 220712 kb
Host smart-2660d73b-668e-4c93-abf9-5c80997e269d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3662916497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3662916497
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.353879303
Short name T919
Test name
Test status
Simulation time 12415712129 ps
CPU time 15.52 seconds
Started May 19 01:55:35 PM PDT 24
Finished May 19 01:55:51 PM PDT 24
Peak memory 216528 kb
Host smart-8e3f22fa-d67d-4fe0-b6e5-ec6baee0e82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353879303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.353879303
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.248080978
Short name T465
Test name
Test status
Simulation time 34967240996 ps
CPU time 12.36 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:56:10 PM PDT 24
Peak memory 216504 kb
Host smart-84df1df3-d899-43c1-a998-ff05d09edb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248080978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.248080978
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3673881442
Short name T663
Test name
Test status
Simulation time 52365094 ps
CPU time 2.52 seconds
Started May 19 01:55:42 PM PDT 24
Finished May 19 01:55:46 PM PDT 24
Peak memory 216452 kb
Host smart-a12e4ca8-e8b3-4a20-aed6-97a72ea2a256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673881442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3673881442
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2398109351
Short name T104
Test name
Test status
Simulation time 108624379 ps
CPU time 0.83 seconds
Started May 19 01:55:40 PM PDT 24
Finished May 19 01:55:41 PM PDT 24
Peak memory 205836 kb
Host smart-0fa3707a-e99a-4639-8c22-b40dfa99b61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398109351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2398109351
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2276859070
Short name T51
Test name
Test status
Simulation time 184785586 ps
CPU time 2.54 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:56:01 PM PDT 24
Peak memory 224292 kb
Host smart-a8cf3f18-a550-4969-970a-42d1692e6037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276859070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2276859070
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.291803087
Short name T850
Test name
Test status
Simulation time 39167123 ps
CPU time 0.76 seconds
Started May 19 01:55:39 PM PDT 24
Finished May 19 01:55:41 PM PDT 24
Peak memory 205376 kb
Host smart-114612dd-8205-4eee-ba3b-3e8c9e6bdcc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291803087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.291803087
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.634748568
Short name T725
Test name
Test status
Simulation time 77655719 ps
CPU time 2.53 seconds
Started May 19 01:55:46 PM PDT 24
Finished May 19 01:55:53 PM PDT 24
Peak memory 235312 kb
Host smart-267700ad-404f-478c-8b0a-80efcabb4d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634748568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.634748568
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3708761686
Short name T887
Test name
Test status
Simulation time 32444635 ps
CPU time 0.75 seconds
Started May 19 01:55:44 PM PDT 24
Finished May 19 01:55:46 PM PDT 24
Peak memory 205448 kb
Host smart-92ce8470-bbcd-4e22-818f-0dbddac81d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708761686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3708761686
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1152801283
Short name T819
Test name
Test status
Simulation time 1935924937 ps
CPU time 16.05 seconds
Started May 19 01:55:54 PM PDT 24
Finished May 19 01:56:17 PM PDT 24
Peak memory 224588 kb
Host smart-0acec923-27d8-4205-ac7d-a0e8f483eb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152801283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1152801283
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2833822130
Short name T230
Test name
Test status
Simulation time 346393854027 ps
CPU time 768.81 seconds
Started May 19 01:55:41 PM PDT 24
Finished May 19 02:08:31 PM PDT 24
Peak memory 254140 kb
Host smart-2a7d111e-e560-44c1-a991-871d75531794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833822130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2833822130
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3682120094
Short name T280
Test name
Test status
Simulation time 8925260339 ps
CPU time 93.71 seconds
Started May 19 01:55:41 PM PDT 24
Finished May 19 01:57:15 PM PDT 24
Peak memory 257412 kb
Host smart-93995702-b394-4b2d-a76b-814ed0992302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682120094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3682120094
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2315213118
Short name T927
Test name
Test status
Simulation time 113986515 ps
CPU time 3.7 seconds
Started May 19 01:55:34 PM PDT 24
Finished May 19 01:55:38 PM PDT 24
Peak memory 224524 kb
Host smart-221a26e7-1212-4673-b25d-b934f4c59ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315213118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2315213118
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.698574445
Short name T686
Test name
Test status
Simulation time 1022201155 ps
CPU time 4.58 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:56:01 PM PDT 24
Peak memory 232752 kb
Host smart-f395df2a-f07e-4e59-9ea0-b51a7d00dec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698574445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.698574445
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2812980884
Short name T702
Test name
Test status
Simulation time 1153775399 ps
CPU time 12.87 seconds
Started May 19 01:55:30 PM PDT 24
Finished May 19 01:55:44 PM PDT 24
Peak memory 232756 kb
Host smart-9bcc6418-55b1-483e-aa6b-8d8581efa6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812980884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2812980884
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1327440976
Short name T827
Test name
Test status
Simulation time 10037760783 ps
CPU time 10.4 seconds
Started May 19 01:55:41 PM PDT 24
Finished May 19 01:55:53 PM PDT 24
Peak memory 218064 kb
Host smart-b81e9eec-26c5-4aab-aa46-49b16db895c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327440976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1327440976
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3848506338
Short name T372
Test name
Test status
Simulation time 176513550 ps
CPU time 2.4 seconds
Started May 19 01:55:42 PM PDT 24
Finished May 19 01:55:45 PM PDT 24
Peak memory 221272 kb
Host smart-b1105779-27e0-4947-aa9f-99ab058969d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848506338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3848506338
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3599612533
Short name T456
Test name
Test status
Simulation time 223115006 ps
CPU time 4.05 seconds
Started May 19 01:55:40 PM PDT 24
Finished May 19 01:55:45 PM PDT 24
Peak memory 221916 kb
Host smart-3785220a-afc6-4c79-a185-423e20e7c2ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3599612533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3599612533
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.4027300429
Short name T884
Test name
Test status
Simulation time 3002146208 ps
CPU time 13.18 seconds
Started May 19 01:55:37 PM PDT 24
Finished May 19 01:55:51 PM PDT 24
Peak memory 216524 kb
Host smart-861abb7e-5888-4fd5-87ae-bd647111e437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027300429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.4027300429
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.851599004
Short name T383
Test name
Test status
Simulation time 3960932889 ps
CPU time 5.35 seconds
Started May 19 01:55:35 PM PDT 24
Finished May 19 01:55:41 PM PDT 24
Peak memory 216488 kb
Host smart-ff3e199f-f986-44cb-a655-6d45d063c24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851599004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.851599004
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.885501574
Short name T501
Test name
Test status
Simulation time 22047687 ps
CPU time 0.7 seconds
Started May 19 01:55:45 PM PDT 24
Finished May 19 01:55:50 PM PDT 24
Peak memory 205852 kb
Host smart-52940b26-3d64-4d17-afe4-b44efc6b2bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885501574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.885501574
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1444993374
Short name T534
Test name
Test status
Simulation time 59485813 ps
CPU time 0.81 seconds
Started May 19 01:55:40 PM PDT 24
Finished May 19 01:55:41 PM PDT 24
Peak memory 205812 kb
Host smart-bcfafe2b-836a-408c-8514-25f8106cdaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444993374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1444993374
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.51918468
Short name T718
Test name
Test status
Simulation time 1119613530 ps
CPU time 6.86 seconds
Started May 19 01:55:29 PM PDT 24
Finished May 19 01:55:37 PM PDT 24
Peak memory 234432 kb
Host smart-26ed6b69-4b62-4789-bd32-46f24e388bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51918468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.51918468
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.872568908
Short name T471
Test name
Test status
Simulation time 13268927 ps
CPU time 0.73 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:55:56 PM PDT 24
Peak memory 204624 kb
Host smart-18a6d821-6be2-46bd-8319-e07f046c064f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872568908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.872568908
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1142819250
Short name T755
Test name
Test status
Simulation time 258569677 ps
CPU time 2.54 seconds
Started May 19 01:55:41 PM PDT 24
Finished May 19 01:55:45 PM PDT 24
Peak memory 233816 kb
Host smart-f8714c8f-ccbc-4ce9-abf3-7ba1f25887bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142819250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1142819250
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1836629382
Short name T60
Test name
Test status
Simulation time 31051638 ps
CPU time 0.74 seconds
Started May 19 01:55:45 PM PDT 24
Finished May 19 01:55:50 PM PDT 24
Peak memory 205768 kb
Host smart-6505180a-40a2-4e0a-a3d7-5ea7abb770b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836629382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1836629382
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2611722357
Short name T685
Test name
Test status
Simulation time 27263006952 ps
CPU time 126.04 seconds
Started May 19 01:55:40 PM PDT 24
Finished May 19 01:57:47 PM PDT 24
Peak memory 249296 kb
Host smart-20482c97-3fe3-40a4-b6b7-1d02a89ee994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611722357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2611722357
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3067955417
Short name T868
Test name
Test status
Simulation time 3301874105 ps
CPU time 14.62 seconds
Started May 19 01:55:45 PM PDT 24
Finished May 19 01:56:02 PM PDT 24
Peak memory 224684 kb
Host smart-e7f8cf95-696c-4af3-94fd-d3f9e9fd5364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067955417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3067955417
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1380966801
Short name T10
Test name
Test status
Simulation time 2960289592 ps
CPU time 11.41 seconds
Started May 19 01:55:37 PM PDT 24
Finished May 19 01:55:50 PM PDT 24
Peak memory 224580 kb
Host smart-0333a985-c591-4664-8695-dcac0149eacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380966801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1380966801
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3110652800
Short name T210
Test name
Test status
Simulation time 18304382504 ps
CPU time 44.41 seconds
Started May 19 01:55:45 PM PDT 24
Finished May 19 01:56:32 PM PDT 24
Peak memory 239196 kb
Host smart-228c4d56-d88b-4277-8caf-94d20d44bd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110652800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3110652800
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2421357888
Short name T644
Test name
Test status
Simulation time 121061024 ps
CPU time 2.34 seconds
Started May 19 01:55:46 PM PDT 24
Finished May 19 01:55:52 PM PDT 24
Peak memory 221404 kb
Host smart-23257a93-d981-432d-8f89-dfe138df3a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421357888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2421357888
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2173619451
Short name T594
Test name
Test status
Simulation time 710140832 ps
CPU time 4.49 seconds
Started May 19 01:55:45 PM PDT 24
Finished May 19 01:55:52 PM PDT 24
Peak memory 217736 kb
Host smart-657cf559-a9bc-4c9f-9b50-6fa85c4d6ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173619451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2173619451
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3254988872
Short name T538
Test name
Test status
Simulation time 4488168361 ps
CPU time 12.45 seconds
Started May 19 01:55:37 PM PDT 24
Finished May 19 01:55:51 PM PDT 24
Peak memory 218984 kb
Host smart-adfa2192-baa3-43c1-ac5e-ef3313bcc841
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3254988872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3254988872
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.4179397263
Short name T161
Test name
Test status
Simulation time 7156919714 ps
CPU time 55.92 seconds
Started May 19 01:55:32 PM PDT 24
Finished May 19 01:56:29 PM PDT 24
Peak memory 241152 kb
Host smart-6dd59ad8-590b-43d7-a18a-03e375a3f3d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179397263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.4179397263
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1282874362
Short name T20
Test name
Test status
Simulation time 4212908510 ps
CPU time 24.5 seconds
Started May 19 01:55:42 PM PDT 24
Finished May 19 01:56:07 PM PDT 24
Peak memory 216556 kb
Host smart-5a9994a1-259f-4eb6-aa12-e5a000718c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282874362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1282874362
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.4110286139
Short name T960
Test name
Test status
Simulation time 3024380127 ps
CPU time 2.7 seconds
Started May 19 01:55:33 PM PDT 24
Finished May 19 01:55:36 PM PDT 24
Peak memory 207944 kb
Host smart-f85a9860-16b3-4bcb-9619-00b66e9c617b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110286139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.4110286139
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.642301754
Short name T752
Test name
Test status
Simulation time 68831113 ps
CPU time 1.2 seconds
Started May 19 01:55:46 PM PDT 24
Finished May 19 01:55:53 PM PDT 24
Peak memory 216420 kb
Host smart-857f6f07-6f05-4586-a499-bce7cb928521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642301754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.642301754
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2904078421
Short name T524
Test name
Test status
Simulation time 23090997 ps
CPU time 0.77 seconds
Started May 19 01:55:46 PM PDT 24
Finished May 19 01:55:52 PM PDT 24
Peak memory 205792 kb
Host smart-ef4179bd-778a-42ca-839f-fe87cf931f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904078421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2904078421
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3244904242
Short name T195
Test name
Test status
Simulation time 670518401 ps
CPU time 6.16 seconds
Started May 19 01:55:44 PM PDT 24
Finished May 19 01:55:51 PM PDT 24
Peak memory 233448 kb
Host smart-d9cd9fa7-9bca-4647-9261-9f01f13171e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244904242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3244904242
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.121751164
Short name T835
Test name
Test status
Simulation time 38498172 ps
CPU time 0.69 seconds
Started May 19 01:55:45 PM PDT 24
Finished May 19 01:55:48 PM PDT 24
Peak memory 205396 kb
Host smart-3b13ba34-23a5-4ed4-ae98-99193191c52a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121751164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.121751164
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4077832769
Short name T437
Test name
Test status
Simulation time 4020321327 ps
CPU time 7.86 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:56:06 PM PDT 24
Peak memory 237272 kb
Host smart-82a78b30-fd3e-453b-8e30-d808028ae9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077832769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4077832769
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3007263643
Short name T556
Test name
Test status
Simulation time 34539619 ps
CPU time 0.77 seconds
Started May 19 01:55:37 PM PDT 24
Finished May 19 01:55:39 PM PDT 24
Peak memory 206440 kb
Host smart-e70cc899-abfc-4834-9f9c-f16322427da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007263643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3007263643
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1370179846
Short name T287
Test name
Test status
Simulation time 7547965906 ps
CPU time 62.5 seconds
Started May 19 01:55:49 PM PDT 24
Finished May 19 01:57:00 PM PDT 24
Peak memory 237684 kb
Host smart-e3bcc193-ee86-4b2a-9b50-e01834238083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370179846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1370179846
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2073696062
Short name T362
Test name
Test status
Simulation time 4330658560 ps
CPU time 3.46 seconds
Started May 19 01:55:51 PM PDT 24
Finished May 19 01:56:03 PM PDT 24
Peak memory 217660 kb
Host smart-8d8bc441-bb55-4754-bd63-3b599cb1e1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073696062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2073696062
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2306861505
Short name T821
Test name
Test status
Simulation time 514864380 ps
CPU time 11.9 seconds
Started May 19 01:55:44 PM PDT 24
Finished May 19 01:55:58 PM PDT 24
Peak memory 232892 kb
Host smart-e2122383-867c-4b85-9aa5-9ff8e8df1d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306861505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2306861505
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1749013481
Short name T529
Test name
Test status
Simulation time 4646982453 ps
CPU time 30.47 seconds
Started May 19 01:55:45 PM PDT 24
Finished May 19 01:56:20 PM PDT 24
Peak memory 232888 kb
Host smart-403b8741-9d61-4511-badd-d0537f829935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749013481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1749013481
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3684981476
Short name T46
Test name
Test status
Simulation time 2299217624 ps
CPU time 22.99 seconds
Started May 19 01:55:46 PM PDT 24
Finished May 19 01:56:14 PM PDT 24
Peak memory 233796 kb
Host smart-37a07a9d-7833-4058-8cd5-0b078c752c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684981476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3684981476
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1484946132
Short name T774
Test name
Test status
Simulation time 41998104823 ps
CPU time 86.68 seconds
Started May 19 01:55:49 PM PDT 24
Finished May 19 01:57:24 PM PDT 24
Peak memory 246416 kb
Host smart-640339fe-6ad0-4194-8531-a8ca563d6b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484946132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1484946132
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2707422441
Short name T270
Test name
Test status
Simulation time 2602528485 ps
CPU time 8.55 seconds
Started May 19 01:55:42 PM PDT 24
Finished May 19 01:55:52 PM PDT 24
Peak memory 234416 kb
Host smart-1e54d0ac-1c9c-4939-aadb-e718e6e6e84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707422441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2707422441
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3482700935
Short name T726
Test name
Test status
Simulation time 3378575391 ps
CPU time 12.04 seconds
Started May 19 01:55:41 PM PDT 24
Finished May 19 01:55:54 PM PDT 24
Peak memory 233208 kb
Host smart-8f272bf5-cd2b-4ace-a022-29774c05f3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482700935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3482700935
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.511628576
Short name T432
Test name
Test status
Simulation time 944650631 ps
CPU time 10.71 seconds
Started May 19 01:55:52 PM PDT 24
Finished May 19 01:56:11 PM PDT 24
Peak memory 219016 kb
Host smart-24abc891-a9c4-4e0a-80bd-d4cb69a1bb3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=511628576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.511628576
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2671391541
Short name T271
Test name
Test status
Simulation time 40033112997 ps
CPU time 119.72 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:57:58 PM PDT 24
Peak memory 257252 kb
Host smart-70f66588-6c09-4746-9a02-52704f8f638f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671391541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2671391541
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.612135502
Short name T59
Test name
Test status
Simulation time 3420147615 ps
CPU time 3.89 seconds
Started May 19 01:55:44 PM PDT 24
Finished May 19 01:55:50 PM PDT 24
Peak memory 219840 kb
Host smart-6c8254f3-e760-4ffb-9e36-00c558b70118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612135502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.612135502
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3577185459
Short name T759
Test name
Test status
Simulation time 2985463924 ps
CPU time 5.57 seconds
Started May 19 01:55:44 PM PDT 24
Finished May 19 01:55:51 PM PDT 24
Peak memory 216556 kb
Host smart-5cbe630a-9ea4-41d7-a3da-e32ebbe72986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577185459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3577185459
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3761014473
Short name T521
Test name
Test status
Simulation time 1890291657 ps
CPU time 9.33 seconds
Started May 19 01:55:37 PM PDT 24
Finished May 19 01:55:48 PM PDT 24
Peak memory 216352 kb
Host smart-56134131-7840-4549-b84e-258865f38ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761014473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3761014473
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1821856072
Short name T86
Test name
Test status
Simulation time 39037239 ps
CPU time 0.79 seconds
Started May 19 01:55:44 PM PDT 24
Finished May 19 01:55:47 PM PDT 24
Peak memory 205860 kb
Host smart-b2bea547-2766-4ee7-b592-de63c088e956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821856072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1821856072
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.959925899
Short name T215
Test name
Test status
Simulation time 8607316515 ps
CPU time 8.66 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:56:02 PM PDT 24
Peak memory 228104 kb
Host smart-acf73469-5332-42e2-94c6-d4e8350ba48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959925899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.959925899
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3819925943
Short name T939
Test name
Test status
Simulation time 116797206 ps
CPU time 0.71 seconds
Started May 19 01:55:58 PM PDT 24
Finished May 19 01:56:04 PM PDT 24
Peak memory 205712 kb
Host smart-df45f3a8-55a1-4daf-a153-588fc0ce1da1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819925943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3819925943
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2100554654
Short name T618
Test name
Test status
Simulation time 31779495 ps
CPU time 2.32 seconds
Started May 19 01:55:43 PM PDT 24
Finished May 19 01:55:47 PM PDT 24
Peak memory 234396 kb
Host smart-20022751-eeba-41b8-be5f-fc43817bd610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100554654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2100554654
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1934089494
Short name T464
Test name
Test status
Simulation time 48049987 ps
CPU time 0.75 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:55:59 PM PDT 24
Peak memory 205464 kb
Host smart-b755cff6-11c6-405d-b55d-907c2fe0dc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934089494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1934089494
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.923050509
Short name T443
Test name
Test status
Simulation time 12867497245 ps
CPU time 109.89 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:57:48 PM PDT 24
Peak memory 257476 kb
Host smart-31451b9f-a8fe-49be-8311-d5644e7bbbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923050509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.923050509
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2253840109
Short name T624
Test name
Test status
Simulation time 390495643809 ps
CPU time 342.78 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 02:01:37 PM PDT 24
Peak memory 254892 kb
Host smart-c5a8f0de-ad0e-4ad4-b30d-3d8c6b5b8fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253840109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2253840109
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.4096488215
Short name T944
Test name
Test status
Simulation time 3749003029 ps
CPU time 60.91 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:56:56 PM PDT 24
Peak memory 250300 kb
Host smart-c7e3ed1d-5c6b-4f7f-85f2-cf455aebf72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096488215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.4096488215
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3859024694
Short name T171
Test name
Test status
Simulation time 874766953 ps
CPU time 6.79 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:56:02 PM PDT 24
Peak memory 232752 kb
Host smart-94fedab5-4924-47a1-902b-b6ac5759975b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859024694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3859024694
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.29781156
Short name T90
Test name
Test status
Simulation time 23664711239 ps
CPU time 26.32 seconds
Started May 19 01:55:46 PM PDT 24
Finished May 19 01:56:17 PM PDT 24
Peak memory 234396 kb
Host smart-ca068994-41d5-4a50-a9c8-6031ac5ae99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29781156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.29781156
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2331778889
Short name T229
Test name
Test status
Simulation time 493847555 ps
CPU time 8.14 seconds
Started May 19 01:55:49 PM PDT 24
Finished May 19 01:56:06 PM PDT 24
Peak memory 218628 kb
Host smart-915fffe4-c322-42d0-b2ed-2b2792097755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331778889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2331778889
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3707316576
Short name T920
Test name
Test status
Simulation time 1136475929 ps
CPU time 4.61 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:55:58 PM PDT 24
Peak memory 218960 kb
Host smart-64c9dc33-387a-4933-9194-c84a3cda1afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707316576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3707316576
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2677851167
Short name T64
Test name
Test status
Simulation time 5764816591 ps
CPU time 17.55 seconds
Started May 19 01:55:49 PM PDT 24
Finished May 19 01:56:15 PM PDT 24
Peak memory 232436 kb
Host smart-b90802c6-d8ef-4eb4-acbc-f3c8a3db65bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677851167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2677851167
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2487425020
Short name T602
Test name
Test status
Simulation time 258550959 ps
CPU time 4.99 seconds
Started May 19 01:55:49 PM PDT 24
Finished May 19 01:56:02 PM PDT 24
Peak memory 222712 kb
Host smart-44b1bfad-7b3b-4932-8b3f-47414d570df1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2487425020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2487425020
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.4060937983
Short name T282
Test name
Test status
Simulation time 81341565227 ps
CPU time 201.89 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:59:19 PM PDT 24
Peak memory 249392 kb
Host smart-9998261f-4200-4f4e-b223-69efeee8d1f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060937983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.4060937983
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.4083507632
Short name T50
Test name
Test status
Simulation time 30072145140 ps
CPU time 38.05 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:56:33 PM PDT 24
Peak memory 216356 kb
Host smart-a6320d24-98ab-4af3-a56b-386a5146185d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083507632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.4083507632
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.926834424
Short name T407
Test name
Test status
Simulation time 1810404113 ps
CPU time 9.24 seconds
Started May 19 01:55:45 PM PDT 24
Finished May 19 01:55:59 PM PDT 24
Peak memory 216404 kb
Host smart-7bd0f31a-5df5-4458-b5fd-f985a79ec89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926834424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.926834424
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3715867612
Short name T454
Test name
Test status
Simulation time 86927802 ps
CPU time 1.57 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:55:55 PM PDT 24
Peak memory 216372 kb
Host smart-570d7b58-303f-4feb-b739-7f29d5ad9552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715867612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3715867612
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2718516895
Short name T576
Test name
Test status
Simulation time 96609867 ps
CPU time 0.88 seconds
Started May 19 01:55:45 PM PDT 24
Finished May 19 01:55:48 PM PDT 24
Peak memory 206832 kb
Host smart-dd18a37d-86af-40eb-99bb-97faf88a4ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718516895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2718516895
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1688589176
Short name T476
Test name
Test status
Simulation time 1019181360 ps
CPU time 6.2 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:56:02 PM PDT 24
Peak memory 233480 kb
Host smart-8d98ed1f-94ea-4cab-8e45-0e26c6f6bce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688589176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1688589176
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3277395788
Short name T740
Test name
Test status
Simulation time 38718287 ps
CPU time 0.7 seconds
Started May 19 01:55:42 PM PDT 24
Finished May 19 01:55:44 PM PDT 24
Peak memory 205372 kb
Host smart-3223ae1b-229f-44f4-b5bc-3c8193a0abaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277395788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3277395788
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.223308309
Short name T108
Test name
Test status
Simulation time 27008685301 ps
CPU time 15.03 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:56:10 PM PDT 24
Peak memory 218712 kb
Host smart-81d06373-7e9c-4ac8-b127-b968da2be2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223308309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.223308309
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1475637308
Short name T952
Test name
Test status
Simulation time 30130020 ps
CPU time 0.84 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:55:59 PM PDT 24
Peak memory 206776 kb
Host smart-42fb4eca-3011-4b07-bf09-f51dd096a1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475637308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1475637308
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.476775465
Short name T263
Test name
Test status
Simulation time 6127005364 ps
CPU time 31.49 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:56:30 PM PDT 24
Peak memory 239756 kb
Host smart-6d36ad04-219f-495f-88dd-eed91310c4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476775465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.476775465
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.869359171
Short name T520
Test name
Test status
Simulation time 36019060976 ps
CPU time 342.03 seconds
Started May 19 01:55:45 PM PDT 24
Finished May 19 02:01:30 PM PDT 24
Peak memory 249532 kb
Host smart-3a358687-232b-4b9c-8dfa-fbdfd7405435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869359171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.869359171
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.506800385
Short name T779
Test name
Test status
Simulation time 25173445003 ps
CPU time 219.25 seconds
Started May 19 01:55:51 PM PDT 24
Finished May 19 01:59:39 PM PDT 24
Peak memory 268616 kb
Host smart-c23c133f-a5fd-42be-9c1f-bf7016db9796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506800385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.506800385
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.4127377757
Short name T660
Test name
Test status
Simulation time 1264171190 ps
CPU time 7.27 seconds
Started May 19 01:55:45 PM PDT 24
Finished May 19 01:55:57 PM PDT 24
Peak memory 241180 kb
Host smart-368ae357-d5e4-4135-aa0d-8342f134d4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127377757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.4127377757
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3331654941
Short name T820
Test name
Test status
Simulation time 1825283263 ps
CPU time 6.42 seconds
Started May 19 01:56:11 PM PDT 24
Finished May 19 01:56:18 PM PDT 24
Peak memory 219688 kb
Host smart-d97a17e6-c9a6-4984-b21d-c432cbf50067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331654941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3331654941
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2799957238
Short name T216
Test name
Test status
Simulation time 3914075405 ps
CPU time 16.31 seconds
Started May 19 01:55:44 PM PDT 24
Finished May 19 01:56:02 PM PDT 24
Peak memory 248752 kb
Host smart-630ce039-70d0-4126-b4b4-2043f4403a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799957238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2799957238
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.18999361
Short name T339
Test name
Test status
Simulation time 4170446399 ps
CPU time 13.85 seconds
Started May 19 01:55:49 PM PDT 24
Finished May 19 01:56:12 PM PDT 24
Peak memory 240508 kb
Host smart-74ab142d-7ad7-48ac-a52a-1eab0495d0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18999361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.18999361
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3601839284
Short name T220
Test name
Test status
Simulation time 15123061169 ps
CPU time 10.77 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:56:05 PM PDT 24
Peak memory 220016 kb
Host smart-6195958d-7cba-4573-9c51-f8135a080ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601839284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3601839284
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2641778889
Short name T54
Test name
Test status
Simulation time 752853558 ps
CPU time 6.09 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:56:00 PM PDT 24
Peak memory 220552 kb
Host smart-f0c253ca-ce90-4c81-9e5b-0099a4d2ee72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2641778889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2641778889
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3324614336
Short name T264
Test name
Test status
Simulation time 230390664550 ps
CPU time 392.17 seconds
Started May 19 01:55:46 PM PDT 24
Finished May 19 02:02:22 PM PDT 24
Peak memory 255236 kb
Host smart-818a2a1e-9f41-48b5-a97b-362d9567cfa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324614336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3324614336
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2534235798
Short name T545
Test name
Test status
Simulation time 5326042225 ps
CPU time 20.82 seconds
Started May 19 01:55:55 PM PDT 24
Finished May 19 01:56:23 PM PDT 24
Peak memory 216280 kb
Host smart-b2100aa1-b60f-45c2-bf3f-6f2b74a1d283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534235798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2534235798
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1581696811
Short name T630
Test name
Test status
Simulation time 651899255 ps
CPU time 3.82 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:55:59 PM PDT 24
Peak memory 216252 kb
Host smart-95a5d3da-d990-4e16-b78b-f71929b25c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581696811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1581696811
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1051374350
Short name T484
Test name
Test status
Simulation time 49794975 ps
CPU time 1.22 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:56:00 PM PDT 24
Peak memory 216584 kb
Host smart-894ad55f-9537-4cd0-8aaa-7b20d2cc0220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051374350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1051374350
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.719050246
Short name T601
Test name
Test status
Simulation time 71934584 ps
CPU time 0.74 seconds
Started May 19 01:55:51 PM PDT 24
Finished May 19 01:56:00 PM PDT 24
Peak memory 205824 kb
Host smart-7b295a3c-c4ef-4374-9853-4e467258a639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719050246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.719050246
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.4187133367
Short name T842
Test name
Test status
Simulation time 1255685102 ps
CPU time 4.41 seconds
Started May 19 01:55:46 PM PDT 24
Finished May 19 01:55:56 PM PDT 24
Peak memory 217628 kb
Host smart-b3e6ab79-5db4-40a7-8161-d17e0f493cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187133367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.4187133367
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3572456782
Short name T830
Test name
Test status
Simulation time 61864080 ps
CPU time 0.71 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:55:58 PM PDT 24
Peak memory 205332 kb
Host smart-2ef98a6d-0434-4c47-aece-1818913951d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572456782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3572456782
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2749001815
Short name T958
Test name
Test status
Simulation time 607942615 ps
CPU time 2.38 seconds
Started May 19 01:56:05 PM PDT 24
Finished May 19 01:56:09 PM PDT 24
Peak memory 218504 kb
Host smart-501d11bf-9d19-4892-a5d7-8c5678e99847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749001815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2749001815
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2609388640
Short name T408
Test name
Test status
Simulation time 27064509 ps
CPU time 0.76 seconds
Started May 19 01:55:46 PM PDT 24
Finished May 19 01:55:52 PM PDT 24
Peak memory 205412 kb
Host smart-01d51b25-33c8-4e4d-91b5-807969088431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609388640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2609388640
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3008894770
Short name T312
Test name
Test status
Simulation time 10361719927 ps
CPU time 76.49 seconds
Started May 19 01:55:46 PM PDT 24
Finished May 19 01:57:07 PM PDT 24
Peak memory 240984 kb
Host smart-7ebd0694-3890-42f7-bce0-69fc01e1197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008894770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3008894770
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2065387672
Short name T237
Test name
Test status
Simulation time 37467313692 ps
CPU time 346.52 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 02:01:46 PM PDT 24
Peak memory 252056 kb
Host smart-145d879d-0529-495b-b9c6-81d41d0e221d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065387672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2065387672
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.322840343
Short name T906
Test name
Test status
Simulation time 3046012767 ps
CPU time 16.44 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:56:12 PM PDT 24
Peak memory 241128 kb
Host smart-dd45c060-39cb-434d-8780-fbb3bddeec0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322840343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.322840343
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3752287992
Short name T728
Test name
Test status
Simulation time 6793503437 ps
CPU time 14.36 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:56:11 PM PDT 24
Peak memory 218768 kb
Host smart-54d9ec8f-5731-4cf5-b3a6-b5b1dbd14b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752287992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3752287992
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3886766069
Short name T247
Test name
Test status
Simulation time 36300549223 ps
CPU time 65.08 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:57:01 PM PDT 24
Peak memory 239860 kb
Host smart-76b714bd-61be-4186-a66b-1b28f8d93318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886766069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3886766069
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3465498202
Short name T945
Test name
Test status
Simulation time 18149830526 ps
CPU time 24.46 seconds
Started May 19 01:55:52 PM PDT 24
Finished May 19 01:56:25 PM PDT 24
Peak memory 232796 kb
Host smart-de63738f-3aab-4c84-866a-ca296f84c04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465498202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3465498202
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3853070032
Short name T379
Test name
Test status
Simulation time 34295757 ps
CPU time 2.18 seconds
Started May 19 01:55:52 PM PDT 24
Finished May 19 01:56:03 PM PDT 24
Peak memory 221260 kb
Host smart-b048ab11-5e58-4bb2-9d3f-49baedf0fd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853070032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3853070032
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.4095614198
Short name T175
Test name
Test status
Simulation time 1085554007 ps
CPU time 5.6 seconds
Started May 19 01:55:52 PM PDT 24
Finished May 19 01:56:05 PM PDT 24
Peak memory 222932 kb
Host smart-df37d011-0e6a-4d2f-96a2-b2121f640311
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4095614198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.4095614198
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1248941917
Short name T863
Test name
Test status
Simulation time 1875276970 ps
CPU time 5.14 seconds
Started May 19 01:55:46 PM PDT 24
Finished May 19 01:55:57 PM PDT 24
Peak memory 216480 kb
Host smart-db1d01e4-c58c-4da1-8781-4bc8009a3bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248941917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1248941917
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2070857460
Short name T395
Test name
Test status
Simulation time 70783429 ps
CPU time 1.1 seconds
Started May 19 01:55:49 PM PDT 24
Finished May 19 01:55:58 PM PDT 24
Peak memory 208048 kb
Host smart-4c7438e8-e21f-48eb-97a8-e820ad00742c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070857460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2070857460
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1956621491
Short name T105
Test name
Test status
Simulation time 38231048 ps
CPU time 0.73 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:55:59 PM PDT 24
Peak memory 205704 kb
Host smart-2d189bd5-1d88-41f4-94c4-7c1b223ab8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956621491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1956621491
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2929741712
Short name T406
Test name
Test status
Simulation time 13379482257 ps
CPU time 19.48 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:56:14 PM PDT 24
Peak memory 235004 kb
Host smart-109fd3e7-e130-4f70-97b6-56340213445d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929741712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2929741712
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3664348804
Short name T554
Test name
Test status
Simulation time 32013183 ps
CPU time 0.77 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:55:57 PM PDT 24
Peak memory 204708 kb
Host smart-3b074dda-174c-44dd-8664-af15f587483a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664348804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3664348804
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3970863052
Short name T803
Test name
Test status
Simulation time 1018953151 ps
CPU time 4.27 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:56:00 PM PDT 24
Peak memory 234404 kb
Host smart-7948b0a2-cc7d-49ad-be33-21a54dbce713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970863052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3970863052
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.847838632
Short name T507
Test name
Test status
Simulation time 98598191 ps
CPU time 0.75 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:55:59 PM PDT 24
Peak memory 205376 kb
Host smart-b6b1c740-41f1-4f26-b081-ee44b95fa8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847838632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.847838632
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.884087108
Short name T893
Test name
Test status
Simulation time 50258986 ps
CPU time 0.74 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:55:59 PM PDT 24
Peak memory 215936 kb
Host smart-70be513f-118a-479e-8160-3f59eafbb9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884087108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.884087108
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3739256923
Short name T164
Test name
Test status
Simulation time 32126666531 ps
CPU time 245.88 seconds
Started May 19 01:55:51 PM PDT 24
Finished May 19 02:00:05 PM PDT 24
Peak memory 249428 kb
Host smart-72c1095c-5c54-44e5-921f-0e92ebb5305c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739256923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3739256923
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2037918413
Short name T878
Test name
Test status
Simulation time 21156577591 ps
CPU time 207.2 seconds
Started May 19 01:55:56 PM PDT 24
Finished May 19 01:59:29 PM PDT 24
Peak memory 264968 kb
Host smart-7d0d7c99-16be-4337-9980-66c5b7b482fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037918413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2037918413
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3383444684
Short name T540
Test name
Test status
Simulation time 2221977823 ps
CPU time 21.67 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:56:17 PM PDT 24
Peak memory 241340 kb
Host smart-10cd7c63-1888-4183-9c5d-887e5b34d119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383444684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3383444684
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.515158000
Short name T231
Test name
Test status
Simulation time 3037052748 ps
CPU time 11.12 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:56:10 PM PDT 24
Peak memory 218492 kb
Host smart-b2bcf255-57f5-49f1-9c68-72d4a76b8fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515158000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.515158000
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2408858879
Short name T343
Test name
Test status
Simulation time 1856763323 ps
CPU time 7.92 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:56:04 PM PDT 24
Peak memory 234348 kb
Host smart-46e44e6c-a4da-4e2e-9ac9-47fc40606fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408858879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2408858879
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2979158073
Short name T261
Test name
Test status
Simulation time 447568410 ps
CPU time 3.86 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:55:57 PM PDT 24
Peak memory 218800 kb
Host smart-efaaa088-b7c0-4e66-abaf-11637a49b4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979158073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2979158073
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2793412994
Short name T972
Test name
Test status
Simulation time 2241400528 ps
CPU time 4.05 seconds
Started May 19 01:55:54 PM PDT 24
Finished May 19 01:56:06 PM PDT 24
Peak memory 232908 kb
Host smart-ae1a1627-c2d7-4e3b-8d28-38e2d3435b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793412994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2793412994
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.53609377
Short name T493
Test name
Test status
Simulation time 500079300 ps
CPU time 7.86 seconds
Started May 19 01:55:49 PM PDT 24
Finished May 19 01:56:05 PM PDT 24
Peak memory 222112 kb
Host smart-5eb63360-1de0-4ba5-94cc-46cba8f4d06b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=53609377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direc
t.53609377
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3802917967
Short name T796
Test name
Test status
Simulation time 76491347501 ps
CPU time 224.55 seconds
Started May 19 01:55:52 PM PDT 24
Finished May 19 01:59:45 PM PDT 24
Peak memory 251952 kb
Host smart-c26705c3-4a52-4c2e-b323-dee7aae237df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802917967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3802917967
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1714805443
Short name T771
Test name
Test status
Simulation time 24958172008 ps
CPU time 36.94 seconds
Started May 19 01:55:52 PM PDT 24
Finished May 19 01:56:38 PM PDT 24
Peak memory 216556 kb
Host smart-bbc7e2c1-e37b-409a-95ed-74b5e6441ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714805443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1714805443
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.4139950302
Short name T402
Test name
Test status
Simulation time 15323815186 ps
CPU time 2.52 seconds
Started May 19 01:55:51 PM PDT 24
Finished May 19 01:56:02 PM PDT 24
Peak memory 208060 kb
Host smart-707d1755-186a-4d6d-bfd4-ffb7d547dfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139950302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4139950302
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3881298223
Short name T416
Test name
Test status
Simulation time 137969201 ps
CPU time 1.08 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:55:58 PM PDT 24
Peak memory 208012 kb
Host smart-d8caf2fe-a5fe-4840-a447-5fd912e3f209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881298223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3881298223
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2297768988
Short name T810
Test name
Test status
Simulation time 109270242 ps
CPU time 0.88 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:56:00 PM PDT 24
Peak memory 205824 kb
Host smart-b9271c83-1496-4453-bf29-a75e7de76bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297768988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2297768988
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1576473632
Short name T505
Test name
Test status
Simulation time 1991715124 ps
CPU time 8.16 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:56:02 PM PDT 24
Peak memory 237140 kb
Host smart-deda3c36-80dc-45b5-8513-6ad5e9a643c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576473632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1576473632
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1610207072
Short name T677
Test name
Test status
Simulation time 39124746 ps
CPU time 0.76 seconds
Started May 19 01:55:54 PM PDT 24
Finished May 19 01:56:02 PM PDT 24
Peak memory 204724 kb
Host smart-770a3217-67b3-4a11-a854-46b239e98226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610207072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1610207072
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2364608872
Short name T531
Test name
Test status
Simulation time 29588599 ps
CPU time 2.55 seconds
Started May 19 01:55:49 PM PDT 24
Finished May 19 01:56:00 PM PDT 24
Peak memory 221436 kb
Host smart-5e338e61-7e97-48fa-b143-edbd17f8f2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364608872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2364608872
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3587104412
Short name T550
Test name
Test status
Simulation time 23399198 ps
CPU time 0.77 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:56:00 PM PDT 24
Peak memory 206436 kb
Host smart-3b3b0d99-e5da-4668-851a-d6b8e3879666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587104412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3587104412
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1149814928
Short name T891
Test name
Test status
Simulation time 38905757 ps
CPU time 0.77 seconds
Started May 19 01:55:52 PM PDT 24
Finished May 19 01:56:01 PM PDT 24
Peak memory 215972 kb
Host smart-82267ca4-018b-4510-b4e7-b7b6c66f635b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149814928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1149814928
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1678393650
Short name T57
Test name
Test status
Simulation time 44791845345 ps
CPU time 301.56 seconds
Started May 19 01:55:52 PM PDT 24
Finished May 19 02:01:02 PM PDT 24
Peak memory 273440 kb
Host smart-b58830e4-e3fa-4bd9-802a-2fdbffa57c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678393650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1678393650
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2394130705
Short name T172
Test name
Test status
Simulation time 151878302 ps
CPU time 6.3 seconds
Started May 19 01:55:52 PM PDT 24
Finished May 19 01:56:09 PM PDT 24
Peak memory 240404 kb
Host smart-d3430f74-6111-45e2-b767-f1f3ddfb6165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394130705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2394130705
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.140472450
Short name T307
Test name
Test status
Simulation time 865411496 ps
CPU time 9.74 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:56:05 PM PDT 24
Peak memory 233376 kb
Host smart-4bf9f182-39f5-458d-81ea-96cb554b2b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140472450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.140472450
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3592834169
Short name T866
Test name
Test status
Simulation time 8460421786 ps
CPU time 58.25 seconds
Started May 19 01:55:52 PM PDT 24
Finished May 19 01:56:59 PM PDT 24
Peak memory 233852 kb
Host smart-0aa3ebb3-d5d3-44b7-a4b8-3be9c2fd5991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592834169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3592834169
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3124399316
Short name T288
Test name
Test status
Simulation time 4032853477 ps
CPU time 15.43 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:56:09 PM PDT 24
Peak memory 227044 kb
Host smart-996d578a-cc1f-4630-b65f-49c405eb74f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124399316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3124399316
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2167582079
Short name T979
Test name
Test status
Simulation time 76401491 ps
CPU time 3 seconds
Started May 19 01:55:53 PM PDT 24
Finished May 19 01:56:04 PM PDT 24
Peak memory 235388 kb
Host smart-97720f29-e0b0-4c04-b12b-d8179c4f42a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167582079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2167582079
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3745462441
Short name T394
Test name
Test status
Simulation time 405325196 ps
CPU time 4.16 seconds
Started May 19 01:55:51 PM PDT 24
Finished May 19 01:56:04 PM PDT 24
Peak memory 222332 kb
Host smart-5846409f-83db-492b-b370-e64f2de59b95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3745462441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3745462441
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2862954864
Short name T179
Test name
Test status
Simulation time 70306490807 ps
CPU time 170.56 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:58:50 PM PDT 24
Peak memory 239768 kb
Host smart-ccface3e-9bc4-42ee-8354-21252f7b75c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862954864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2862954864
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2676271484
Short name T873
Test name
Test status
Simulation time 21094016232 ps
CPU time 22.27 seconds
Started May 19 01:55:49 PM PDT 24
Finished May 19 01:56:20 PM PDT 24
Peak memory 216576 kb
Host smart-524c4126-20d2-4f4f-9be8-124b5c753f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676271484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2676271484
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1598038562
Short name T697
Test name
Test status
Simulation time 4016394837 ps
CPU time 2.94 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:55:58 PM PDT 24
Peak memory 216296 kb
Host smart-cbefd90f-760d-4706-b08a-5f148f35840c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598038562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1598038562
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2649989616
Short name T467
Test name
Test status
Simulation time 28364439 ps
CPU time 0.71 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:55:58 PM PDT 24
Peak memory 205524 kb
Host smart-6ab9a772-d444-474c-a6fd-cc5199a1d910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649989616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2649989616
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.327394967
Short name T537
Test name
Test status
Simulation time 17337617 ps
CPU time 0.66 seconds
Started May 19 01:55:51 PM PDT 24
Finished May 19 01:56:00 PM PDT 24
Peak memory 205472 kb
Host smart-f1499ba1-63f8-4a36-ba23-a36ec3639bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327394967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.327394967
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.650442514
Short name T838
Test name
Test status
Simulation time 277284169 ps
CPU time 3.77 seconds
Started May 19 01:55:46 PM PDT 24
Finished May 19 01:55:55 PM PDT 24
Peak memory 222992 kb
Host smart-b711cd7a-e94a-481f-9747-72dc169b764f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650442514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.650442514
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2376693907
Short name T901
Test name
Test status
Simulation time 15566215 ps
CPU time 0.76 seconds
Started May 19 01:56:23 PM PDT 24
Finished May 19 01:56:25 PM PDT 24
Peak memory 204744 kb
Host smart-e05244d8-73d1-4844-a571-7a3a5ed6f290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376693907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2376693907
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3243135181
Short name T843
Test name
Test status
Simulation time 32124102 ps
CPU time 2.02 seconds
Started May 19 01:56:16 PM PDT 24
Finished May 19 01:56:19 PM PDT 24
Peak memory 216156 kb
Host smart-fe6e1abd-3056-4807-b268-f82438c4cae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243135181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3243135181
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1515410213
Short name T544
Test name
Test status
Simulation time 57676915 ps
CPU time 0.86 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:55:56 PM PDT 24
Peak memory 206440 kb
Host smart-22018129-aa71-42da-bad6-a1baa9850323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515410213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1515410213
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1461378662
Short name T510
Test name
Test status
Simulation time 10231766 ps
CPU time 0.73 seconds
Started May 19 01:55:54 PM PDT 24
Finished May 19 01:56:02 PM PDT 24
Peak memory 207756 kb
Host smart-8ec91256-1923-49c9-b552-8e9fbb3a3532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461378662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1461378662
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.718491366
Short name T249
Test name
Test status
Simulation time 36549574766 ps
CPU time 139.75 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:58:13 PM PDT 24
Peak memory 265784 kb
Host smart-fcda4026-b49a-40d6-8c41-6166b7a653e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718491366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.718491366
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3322648641
Short name T266
Test name
Test status
Simulation time 12441684417 ps
CPU time 188.87 seconds
Started May 19 01:55:53 PM PDT 24
Finished May 19 01:59:10 PM PDT 24
Peak memory 249404 kb
Host smart-e9936786-6946-4101-a23c-da7a7412ef0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322648641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3322648641
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.786444383
Short name T7
Test name
Test status
Simulation time 215462670 ps
CPU time 2.95 seconds
Started May 19 01:55:53 PM PDT 24
Finished May 19 01:56:04 PM PDT 24
Peak memory 232768 kb
Host smart-10a51387-16d7-485c-91bf-0983da2742a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786444383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.786444383
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1867994840
Short name T622
Test name
Test status
Simulation time 561883664 ps
CPU time 7.32 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:56:02 PM PDT 24
Peak memory 232784 kb
Host smart-72ab7962-030d-4abc-b62d-a93643558596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867994840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1867994840
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3696000550
Short name T783
Test name
Test status
Simulation time 12844575519 ps
CPU time 74.93 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:57:10 PM PDT 24
Peak memory 239420 kb
Host smart-4b633918-0aa0-4841-88bd-0074e3c24d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696000550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3696000550
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2189231883
Short name T338
Test name
Test status
Simulation time 110440053079 ps
CPU time 27.03 seconds
Started May 19 01:56:18 PM PDT 24
Finished May 19 01:56:46 PM PDT 24
Peak memory 238736 kb
Host smart-0ada8f8e-90c8-44a6-9e55-7579e293f41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189231883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2189231883
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2663734151
Short name T645
Test name
Test status
Simulation time 13796929025 ps
CPU time 10.86 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:56:10 PM PDT 24
Peak memory 237112 kb
Host smart-6b5f937b-1e46-4854-a36d-a6127c4fc46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663734151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2663734151
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2407476305
Short name T52
Test name
Test status
Simulation time 5063339856 ps
CPU time 7.36 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:56:03 PM PDT 24
Peak memory 222540 kb
Host smart-5e521c7a-a372-4a1f-9334-5f1c194cd322
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2407476305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2407476305
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2715220482
Short name T100
Test name
Test status
Simulation time 29013101327 ps
CPU time 95.74 seconds
Started May 19 01:55:54 PM PDT 24
Finished May 19 01:57:37 PM PDT 24
Peak memory 224804 kb
Host smart-2ae13f47-b8c4-4ea5-bf46-a0dabd9a5247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715220482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2715220482
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.43570219
Short name T29
Test name
Test status
Simulation time 18078416979 ps
CPU time 24.94 seconds
Started May 19 01:55:49 PM PDT 24
Finished May 19 01:56:23 PM PDT 24
Peak memory 216752 kb
Host smart-51c0a44a-ca8e-4e0e-9b92-7b1def92f411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43570219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.43570219
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.17541436
Short name T393
Test name
Test status
Simulation time 1403504388 ps
CPU time 5.85 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:56:01 PM PDT 24
Peak memory 216392 kb
Host smart-9c31f6d8-bced-4b59-a5db-6d0b1ab791e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17541436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.17541436
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3774998215
Short name T676
Test name
Test status
Simulation time 125141740 ps
CPU time 1.17 seconds
Started May 19 01:55:51 PM PDT 24
Finished May 19 01:56:04 PM PDT 24
Peak memory 207984 kb
Host smart-b740fb79-017d-4059-9fa9-4ba6aa7bc9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774998215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3774998215
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3394136428
Short name T880
Test name
Test status
Simulation time 34352923 ps
CPU time 0.75 seconds
Started May 19 01:55:49 PM PDT 24
Finished May 19 01:55:58 PM PDT 24
Peak memory 205820 kb
Host smart-e0a9a305-dda4-4449-8252-43de9189cfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394136428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3394136428
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1408205475
Short name T158
Test name
Test status
Simulation time 162277807 ps
CPU time 3.33 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:56:00 PM PDT 24
Peak memory 224540 kb
Host smart-4d246291-552d-4e8e-8e2a-c233a61212e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408205475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1408205475
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2503747441
Short name T770
Test name
Test status
Simulation time 30536064 ps
CPU time 0.76 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:54:55 PM PDT 24
Peak memory 205692 kb
Host smart-d63e526e-2277-4600-9eff-6347f530b6d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503747441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
503747441
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.999373762
Short name T808
Test name
Test status
Simulation time 39849845927 ps
CPU time 18.68 seconds
Started May 19 01:54:43 PM PDT 24
Finished May 19 01:55:04 PM PDT 24
Peak memory 234056 kb
Host smart-68280017-f710-4778-8221-f2bf40617c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999373762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.999373762
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.653590441
Short name T489
Test name
Test status
Simulation time 118619285 ps
CPU time 0.8 seconds
Started May 19 01:54:38 PM PDT 24
Finished May 19 01:54:40 PM PDT 24
Peak memory 206768 kb
Host smart-013ea40f-697b-4fff-a0ad-54ab6dbb507c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653590441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.653590441
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1437596600
Short name T592
Test name
Test status
Simulation time 45509347553 ps
CPU time 162.23 seconds
Started May 19 01:54:36 PM PDT 24
Finished May 19 01:57:19 PM PDT 24
Peak memory 249304 kb
Host smart-88dcfa35-67d3-4a8e-bb50-81085dd0e48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437596600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1437596600
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1738444902
Short name T206
Test name
Test status
Simulation time 7871037002 ps
CPU time 85.36 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:56:25 PM PDT 24
Peak memory 233032 kb
Host smart-d4016542-a179-4c87-b48b-973c930bd41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738444902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1738444902
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2907161007
Short name T910
Test name
Test status
Simulation time 4097230817 ps
CPU time 103.61 seconds
Started May 19 01:54:46 PM PDT 24
Finished May 19 01:56:33 PM PDT 24
Peak memory 254120 kb
Host smart-3c3fcbbd-61bd-497c-84c6-a659ff5d5d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907161007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2907161007
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3629742453
Short name T913
Test name
Test status
Simulation time 2380332602 ps
CPU time 10.02 seconds
Started May 19 01:54:39 PM PDT 24
Finished May 19 01:54:50 PM PDT 24
Peak memory 224724 kb
Host smart-c5f31f47-0ae3-4fcb-9974-ebcfcda33c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629742453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3629742453
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3472716622
Short name T495
Test name
Test status
Simulation time 2926246881 ps
CPU time 9.5 seconds
Started May 19 01:54:43 PM PDT 24
Finished May 19 01:54:54 PM PDT 24
Peak memory 234020 kb
Host smart-3ea49903-6f4b-4b80-9137-e37f70d38ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472716622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3472716622
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2160861128
Short name T235
Test name
Test status
Simulation time 104747771 ps
CPU time 3.66 seconds
Started May 19 01:54:37 PM PDT 24
Finished May 19 01:54:42 PM PDT 24
Peak memory 234816 kb
Host smart-53f8803d-712d-4118-a4eb-2c42f4caaf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160861128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2160861128
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3153252338
Short name T376
Test name
Test status
Simulation time 26766929 ps
CPU time 1.07 seconds
Started May 19 01:54:44 PM PDT 24
Finished May 19 01:54:47 PM PDT 24
Peak memory 217960 kb
Host smart-29ba2ace-c444-4b49-96ae-4f7fd95665e3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153252338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3153252338
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2435987186
Short name T259
Test name
Test status
Simulation time 8975008716 ps
CPU time 22.73 seconds
Started May 19 01:54:36 PM PDT 24
Finished May 19 01:55:00 PM PDT 24
Peak memory 237688 kb
Host smart-c62db31b-bdb9-41dc-bc7c-893f2b1751b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435987186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2435987186
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2040906724
Short name T381
Test name
Test status
Simulation time 50523056 ps
CPU time 1.92 seconds
Started May 19 01:54:44 PM PDT 24
Finished May 19 01:54:48 PM PDT 24
Peak memory 216132 kb
Host smart-d0d55f0c-83ce-488c-931e-c3aa62181c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040906724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2040906724
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2301769545
Short name T463
Test name
Test status
Simulation time 1663305190 ps
CPU time 4.15 seconds
Started May 19 01:54:31 PM PDT 24
Finished May 19 01:54:36 PM PDT 24
Peak memory 222040 kb
Host smart-df88b007-f016-4de1-8010-85bfe79e4d19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2301769545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2301769545
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3558584505
Short name T76
Test name
Test status
Simulation time 310784993 ps
CPU time 1.22 seconds
Started May 19 01:54:43 PM PDT 24
Finished May 19 01:54:46 PM PDT 24
Peak memory 235160 kb
Host smart-18c568fe-e654-4308-a2fc-9a2030de58c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558584505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3558584505
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3777331259
Short name T688
Test name
Test status
Simulation time 308264685 ps
CPU time 1.18 seconds
Started May 19 01:54:40 PM PDT 24
Finished May 19 01:54:42 PM PDT 24
Peak memory 206924 kb
Host smart-92898de5-3c3a-48a4-8029-9162e4e09746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777331259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3777331259
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.4179228887
Short name T351
Test name
Test status
Simulation time 934693035 ps
CPU time 12 seconds
Started May 19 01:54:34 PM PDT 24
Finished May 19 01:54:48 PM PDT 24
Peak memory 216660 kb
Host smart-ff0724b2-1e4f-4e9e-91bc-fbe5d95ac2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179228887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.4179228887
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.739439651
Short name T773
Test name
Test status
Simulation time 2739420146 ps
CPU time 6.04 seconds
Started May 19 01:54:45 PM PDT 24
Finished May 19 01:54:54 PM PDT 24
Peak memory 216408 kb
Host smart-b5712e64-ca62-4689-8aea-1d527debee59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739439651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.739439651
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2403061833
Short name T440
Test name
Test status
Simulation time 770482462 ps
CPU time 9.42 seconds
Started May 19 01:54:40 PM PDT 24
Finished May 19 01:54:50 PM PDT 24
Peak memory 216368 kb
Host smart-0c4da99e-4ad3-4974-8ac2-94a7ae93d7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403061833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2403061833
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.177062937
Short name T744
Test name
Test status
Simulation time 36276712 ps
CPU time 0.82 seconds
Started May 19 01:54:39 PM PDT 24
Finished May 19 01:54:41 PM PDT 24
Peak memory 206844 kb
Host smart-e81e11b7-1997-42f7-8757-035703f5b16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177062937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.177062937
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3808118827
Short name T225
Test name
Test status
Simulation time 4130474676 ps
CPU time 13.42 seconds
Started May 19 01:54:35 PM PDT 24
Finished May 19 01:54:49 PM PDT 24
Peak memory 227776 kb
Host smart-9eef0527-3514-4593-909e-601baa234700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808118827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3808118827
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4208586081
Short name T418
Test name
Test status
Simulation time 35971076 ps
CPU time 0.7 seconds
Started May 19 01:55:55 PM PDT 24
Finished May 19 01:56:02 PM PDT 24
Peak memory 204752 kb
Host smart-b75f1d90-293d-4b93-937c-0de8deb5e643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208586081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4208586081
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2624405702
Short name T926
Test name
Test status
Simulation time 744170760 ps
CPU time 6.98 seconds
Started May 19 01:55:52 PM PDT 24
Finished May 19 01:56:08 PM PDT 24
Peak memory 218576 kb
Host smart-e5cea922-18b9-4788-afad-28c5259e1ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624405702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2624405702
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3575012825
Short name T572
Test name
Test status
Simulation time 67773174 ps
CPU time 0.78 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:55:59 PM PDT 24
Peak memory 206452 kb
Host smart-6b32e445-39af-4dd4-8704-c1df1c757511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575012825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3575012825
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1342715765
Short name T577
Test name
Test status
Simulation time 11290661463 ps
CPU time 89.5 seconds
Started May 19 01:56:00 PM PDT 24
Finished May 19 01:57:34 PM PDT 24
Peak memory 255104 kb
Host smart-5ff551bd-7c70-4c9f-887b-dcfe82a06d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342715765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1342715765
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.4255957634
Short name T553
Test name
Test status
Simulation time 26956745832 ps
CPU time 248.44 seconds
Started May 19 01:55:53 PM PDT 24
Finished May 19 02:00:09 PM PDT 24
Peak memory 249520 kb
Host smart-70edd176-0e53-4bfe-b3a6-c69962bb5619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255957634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.4255957634
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1418493131
Short name T804
Test name
Test status
Simulation time 28129590445 ps
CPU time 151.8 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:58:27 PM PDT 24
Peak memory 240996 kb
Host smart-36af8831-35b5-4647-848b-360d8f198d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418493131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1418493131
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.152285559
Short name T871
Test name
Test status
Simulation time 570326794 ps
CPU time 10.56 seconds
Started May 19 01:56:02 PM PDT 24
Finished May 19 01:56:16 PM PDT 24
Peak memory 249160 kb
Host smart-8103905e-e7d3-4cd3-9b6f-b5653a7b58ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152285559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.152285559
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1594204128
Short name T936
Test name
Test status
Simulation time 175916440 ps
CPU time 2.64 seconds
Started May 19 01:55:54 PM PDT 24
Finished May 19 01:56:04 PM PDT 24
Peak memory 235388 kb
Host smart-32d54611-aac2-4672-ae66-0bb8aa137501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594204128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1594204128
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1289051997
Short name T772
Test name
Test status
Simulation time 3315158545 ps
CPU time 36.07 seconds
Started May 19 01:55:51 PM PDT 24
Finished May 19 01:56:35 PM PDT 24
Peak memory 230996 kb
Host smart-59fbda05-b7da-4f09-a8a8-951a39197144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289051997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1289051997
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.723792149
Short name T272
Test name
Test status
Simulation time 960984487 ps
CPU time 5.57 seconds
Started May 19 01:55:51 PM PDT 24
Finished May 19 01:56:05 PM PDT 24
Peak memory 239328 kb
Host smart-e7e327e8-b6f5-48ab-9dbf-b13cec6510f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723792149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.723792149
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2083961954
Short name T845
Test name
Test status
Simulation time 1959467627 ps
CPU time 12.29 seconds
Started May 19 01:55:51 PM PDT 24
Finished May 19 01:56:12 PM PDT 24
Peak memory 242868 kb
Host smart-ed0f917f-9ad1-4282-aec1-661b760994c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083961954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2083961954
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3933419938
Short name T647
Test name
Test status
Simulation time 1416459040 ps
CPU time 5.98 seconds
Started May 19 01:56:11 PM PDT 24
Finished May 19 01:56:18 PM PDT 24
Peak memory 219864 kb
Host smart-6e301c78-d311-4830-bd08-ed950d239905
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3933419938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3933419938
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.4198421261
Short name T91
Test name
Test status
Simulation time 143187890016 ps
CPU time 710.41 seconds
Started May 19 01:56:12 PM PDT 24
Finished May 19 02:08:03 PM PDT 24
Peak memory 270516 kb
Host smart-ed2daea8-27f3-44d8-963a-10bc2bd78e8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198421261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.4198421261
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.641850072
Short name T439
Test name
Test status
Simulation time 1780486083 ps
CPU time 3.15 seconds
Started May 19 01:55:52 PM PDT 24
Finished May 19 01:56:04 PM PDT 24
Peak memory 216180 kb
Host smart-bfe2b3cc-d35e-48b2-967a-3352e4829485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641850072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.641850072
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1433729379
Short name T528
Test name
Test status
Simulation time 2557488215 ps
CPU time 5.16 seconds
Started May 19 01:55:53 PM PDT 24
Finished May 19 01:56:06 PM PDT 24
Peak memory 216496 kb
Host smart-e28597f4-81c4-4a84-aeb1-5dad212f2a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433729379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1433729379
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3108212470
Short name T423
Test name
Test status
Simulation time 203799601 ps
CPU time 2.83 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:55:58 PM PDT 24
Peak memory 216416 kb
Host smart-1f8837d2-a244-485c-b986-f2fa3e105c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108212470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3108212470
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2798701072
Short name T16
Test name
Test status
Simulation time 54067281 ps
CPU time 0.87 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:55:59 PM PDT 24
Peak memory 205716 kb
Host smart-7e0447c7-9162-4b55-becf-b67db5d95bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798701072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2798701072
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2417474234
Short name T84
Test name
Test status
Simulation time 24144286747 ps
CPU time 18.61 seconds
Started May 19 01:55:52 PM PDT 24
Finished May 19 01:56:19 PM PDT 24
Peak memory 217652 kb
Host smart-7a89af26-de97-42d4-b5d4-4c677413c552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417474234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2417474234
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1539195982
Short name T367
Test name
Test status
Simulation time 37769392 ps
CPU time 0.72 seconds
Started May 19 01:55:51 PM PDT 24
Finished May 19 01:56:00 PM PDT 24
Peak memory 205736 kb
Host smart-c2cbb98d-09c6-4e41-bddf-6d37f3e9ed8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539195982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1539195982
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1069196772
Short name T806
Test name
Test status
Simulation time 66227685 ps
CPU time 2.99 seconds
Started May 19 01:56:05 PM PDT 24
Finished May 19 01:56:09 PM PDT 24
Peak memory 233848 kb
Host smart-3f10f635-9c70-419a-b733-ce56b3204354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069196772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1069196772
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3060784026
Short name T789
Test name
Test status
Simulation time 58825005 ps
CPU time 0.74 seconds
Started May 19 01:55:47 PM PDT 24
Finished May 19 01:55:56 PM PDT 24
Peak memory 206436 kb
Host smart-c1e957f4-d353-42a2-a77e-225780c785e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060784026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3060784026
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1834993655
Short name T864
Test name
Test status
Simulation time 29783907 ps
CPU time 0.76 seconds
Started May 19 01:55:58 PM PDT 24
Finished May 19 01:56:04 PM PDT 24
Peak memory 215976 kb
Host smart-55fb3284-0d99-453e-8881-5a68eab41f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834993655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1834993655
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.431292650
Short name T55
Test name
Test status
Simulation time 12217582671 ps
CPU time 123.32 seconds
Started May 19 01:55:55 PM PDT 24
Finished May 19 01:58:05 PM PDT 24
Peak memory 239944 kb
Host smart-24401522-5cd6-454b-b2c3-00bcc7fa3395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431292650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.431292650
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.415312011
Short name T698
Test name
Test status
Simulation time 27198618313 ps
CPU time 33.62 seconds
Started May 19 01:55:55 PM PDT 24
Finished May 19 01:56:36 PM PDT 24
Peak memory 217596 kb
Host smart-a81d4526-9bf8-4fbb-9486-91a24a97d07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415312011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.415312011
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2438806416
Short name T565
Test name
Test status
Simulation time 384970661 ps
CPU time 10.72 seconds
Started May 19 01:55:59 PM PDT 24
Finished May 19 01:56:14 PM PDT 24
Peak memory 223120 kb
Host smart-c1173b97-aa30-409b-a9fb-f7a4ce56480b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438806416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2438806416
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2752297730
Short name T311
Test name
Test status
Simulation time 10743885309 ps
CPU time 5.91 seconds
Started May 19 01:55:55 PM PDT 24
Finished May 19 01:56:08 PM PDT 24
Peak memory 219428 kb
Host smart-ceabf853-cdba-49b7-ae91-c5e3696c90a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752297730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2752297730
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4059322741
Short name T345
Test name
Test status
Simulation time 1048747537 ps
CPU time 17.58 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:56:14 PM PDT 24
Peak memory 222616 kb
Host smart-b2948e20-a0ed-4f20-90b9-f3426750b07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059322741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4059322741
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.467798504
Short name T242
Test name
Test status
Simulation time 368880258 ps
CPU time 3.06 seconds
Started May 19 01:55:50 PM PDT 24
Finished May 19 01:56:01 PM PDT 24
Peak memory 224472 kb
Host smart-83807a80-8d29-4ede-8e59-c74f3c75b97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467798504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.467798504
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.335838938
Short name T923
Test name
Test status
Simulation time 1371373225 ps
CPU time 6.69 seconds
Started May 19 01:55:55 PM PDT 24
Finished May 19 01:56:08 PM PDT 24
Peak memory 218452 kb
Host smart-a534ea1c-4545-4492-9d0f-97828f9adbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335838938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.335838938
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3861567289
Short name T543
Test name
Test status
Simulation time 2891389785 ps
CPU time 13.16 seconds
Started May 19 01:56:00 PM PDT 24
Finished May 19 01:56:17 PM PDT 24
Peak memory 219340 kb
Host smart-b1f2aeaa-ce10-4738-bd96-ff3af272ac71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3861567289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3861567289
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2906094391
Short name T753
Test name
Test status
Simulation time 331921112 ps
CPU time 1.14 seconds
Started May 19 01:55:48 PM PDT 24
Finished May 19 01:55:58 PM PDT 24
Peak memory 206788 kb
Host smart-db7c774e-d9ba-42a9-8e39-6ad490196d1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906094391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2906094391
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.978009985
Short name T483
Test name
Test status
Simulation time 758969431 ps
CPU time 5.14 seconds
Started May 19 01:56:01 PM PDT 24
Finished May 19 01:56:10 PM PDT 24
Peak memory 216396 kb
Host smart-fb6620dc-5d92-4f48-990f-043ee99197a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978009985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.978009985
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4120644526
Short name T675
Test name
Test status
Simulation time 1602231688 ps
CPU time 2.66 seconds
Started May 19 01:56:01 PM PDT 24
Finished May 19 01:56:07 PM PDT 24
Peak memory 216248 kb
Host smart-6abcf9e5-889e-4837-a87c-d7dbab0595e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120644526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.4120644526
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1529085903
Short name T865
Test name
Test status
Simulation time 76400903 ps
CPU time 1.61 seconds
Started May 19 01:56:04 PM PDT 24
Finished May 19 01:56:08 PM PDT 24
Peak memory 216452 kb
Host smart-f2baf59e-e10d-4fc6-8295-a19052b98001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529085903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1529085903
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.91294141
Short name T61
Test name
Test status
Simulation time 17945663 ps
CPU time 0.8 seconds
Started May 19 01:55:57 PM PDT 24
Finished May 19 01:56:04 PM PDT 24
Peak memory 205780 kb
Host smart-69bf2d56-b61c-4e17-bf18-fd4bb70e9bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91294141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.91294141
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.4175742350
Short name T223
Test name
Test status
Simulation time 79718994599 ps
CPU time 25.86 seconds
Started May 19 01:56:00 PM PDT 24
Finished May 19 01:56:30 PM PDT 24
Peak memory 239308 kb
Host smart-c5b544a8-91bf-4277-b3c1-1fe32a0cf18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175742350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.4175742350
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2278906720
Short name T71
Test name
Test status
Simulation time 29845720 ps
CPU time 0.71 seconds
Started May 19 01:56:14 PM PDT 24
Finished May 19 01:56:16 PM PDT 24
Peak memory 205736 kb
Host smart-b8036a14-1498-47b7-986a-3b0b19c2dc70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278906720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2278906720
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1530477339
Short name T719
Test name
Test status
Simulation time 35598544 ps
CPU time 2.31 seconds
Started May 19 01:55:55 PM PDT 24
Finished May 19 01:56:04 PM PDT 24
Peak memory 221744 kb
Host smart-98eaa882-12bf-43ca-9663-912293fd7137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530477339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1530477339
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.165348032
Short name T512
Test name
Test status
Simulation time 19927911 ps
CPU time 0.8 seconds
Started May 19 01:55:58 PM PDT 24
Finished May 19 01:56:04 PM PDT 24
Peak memory 206432 kb
Host smart-665a3546-60b9-4bc6-9d3b-2396bdc078a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165348032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.165348032
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3912390468
Short name T32
Test name
Test status
Simulation time 253489389894 ps
CPU time 446.81 seconds
Started May 19 01:56:05 PM PDT 24
Finished May 19 02:03:34 PM PDT 24
Peak memory 254072 kb
Host smart-205ce27c-6a9b-4a3a-8427-50b902ac9eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912390468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3912390468
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1520687221
Short name T778
Test name
Test status
Simulation time 13657037161 ps
CPU time 86.76 seconds
Started May 19 01:56:08 PM PDT 24
Finished May 19 01:57:36 PM PDT 24
Peak memory 249388 kb
Host smart-1dfd3c51-21df-4346-bb5a-d253360855a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520687221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1520687221
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3426149990
Short name T764
Test name
Test status
Simulation time 201156644690 ps
CPU time 373.65 seconds
Started May 19 01:55:55 PM PDT 24
Finished May 19 02:02:16 PM PDT 24
Peak memory 249580 kb
Host smart-550e115f-9aef-4e64-b280-b67d6fb71b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426149990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3426149990
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3447487544
Short name T729
Test name
Test status
Simulation time 833174083 ps
CPU time 10.59 seconds
Started May 19 01:55:52 PM PDT 24
Finished May 19 01:56:14 PM PDT 24
Peak memory 233068 kb
Host smart-a95148be-4905-4147-8937-c8ae4a197df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447487544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3447487544
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2875519448
Short name T848
Test name
Test status
Simulation time 591138868 ps
CPU time 5.68 seconds
Started May 19 01:55:52 PM PDT 24
Finished May 19 01:56:06 PM PDT 24
Peak memory 224516 kb
Host smart-77353bf8-ae02-4fc4-a256-6d3089d6ce23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875519448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2875519448
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.26509795
Short name T246
Test name
Test status
Simulation time 55263037655 ps
CPU time 100.89 seconds
Started May 19 01:55:52 PM PDT 24
Finished May 19 01:57:42 PM PDT 24
Peak memory 229192 kb
Host smart-c04777a5-baf9-4128-ac47-761fa3a5d8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26509795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.26509795
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1318294649
Short name T297
Test name
Test status
Simulation time 205054027 ps
CPU time 4.28 seconds
Started May 19 01:56:00 PM PDT 24
Finished May 19 01:56:08 PM PDT 24
Peak memory 228792 kb
Host smart-b56fd356-7a3f-4056-a99e-b3b4dec5b400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318294649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1318294649
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3309994824
Short name T535
Test name
Test status
Simulation time 291193336 ps
CPU time 2.03 seconds
Started May 19 01:56:14 PM PDT 24
Finished May 19 01:56:17 PM PDT 24
Peak memory 216136 kb
Host smart-98373798-366a-438d-9d55-7ade23fdaf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309994824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3309994824
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1009753545
Short name T109
Test name
Test status
Simulation time 278491235 ps
CPU time 5.34 seconds
Started May 19 01:55:57 PM PDT 24
Finished May 19 01:56:08 PM PDT 24
Peak memory 220124 kb
Host smart-48f62133-3008-4c66-ba86-f2aada2e6224
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1009753545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1009753545
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3602022566
Short name T829
Test name
Test status
Simulation time 3717716227 ps
CPU time 12.43 seconds
Started May 19 01:56:00 PM PDT 24
Finished May 19 01:56:17 PM PDT 24
Peak memory 216384 kb
Host smart-df5a9a5d-dd38-4b9f-9fac-842ea2458aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602022566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3602022566
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.115930442
Short name T19
Test name
Test status
Simulation time 12105142308 ps
CPU time 9.64 seconds
Started May 19 01:55:55 PM PDT 24
Finished May 19 01:56:12 PM PDT 24
Peak memory 216568 kb
Host smart-abbfee5d-8fb9-490a-a49d-2257916e0cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115930442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.115930442
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1698275289
Short name T879
Test name
Test status
Simulation time 312734776 ps
CPU time 2.01 seconds
Started May 19 01:56:16 PM PDT 24
Finished May 19 01:56:18 PM PDT 24
Peak memory 216276 kb
Host smart-a38858d4-9594-4551-8ed8-d5267c64334a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698275289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1698275289
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2182585573
Short name T450
Test name
Test status
Simulation time 32847605 ps
CPU time 0.83 seconds
Started May 19 01:56:09 PM PDT 24
Finished May 19 01:56:11 PM PDT 24
Peak memory 205792 kb
Host smart-3e1e85fe-290a-494f-ac78-dd9a5fc8188f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182585573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2182585573
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.587786046
Short name T88
Test name
Test status
Simulation time 1431741095 ps
CPU time 7.43 seconds
Started May 19 01:56:15 PM PDT 24
Finished May 19 01:56:29 PM PDT 24
Peak memory 217336 kb
Host smart-32123b1f-663f-4876-9c13-d75c950308d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587786046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.587786046
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2626710543
Short name T946
Test name
Test status
Simulation time 13459575 ps
CPU time 0.77 seconds
Started May 19 01:56:03 PM PDT 24
Finished May 19 01:56:06 PM PDT 24
Peak memory 205756 kb
Host smart-e631e070-d918-4c51-9e5d-e6f24b361ca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626710543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2626710543
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.599817857
Short name T716
Test name
Test status
Simulation time 911441752 ps
CPU time 2.71 seconds
Started May 19 01:56:18 PM PDT 24
Finished May 19 01:56:21 PM PDT 24
Peak memory 218880 kb
Host smart-f7d59b7a-7bab-44d6-9d00-d4563d5ba8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599817857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.599817857
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3126255716
Short name T430
Test name
Test status
Simulation time 20020932 ps
CPU time 0.76 seconds
Started May 19 01:56:01 PM PDT 24
Finished May 19 01:56:06 PM PDT 24
Peak memory 206824 kb
Host smart-7586b914-6e38-42af-b3e5-99a752a98162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126255716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3126255716
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.4092014334
Short name T62
Test name
Test status
Simulation time 14831722385 ps
CPU time 61.31 seconds
Started May 19 01:56:15 PM PDT 24
Finished May 19 01:57:17 PM PDT 24
Peak memory 256956 kb
Host smart-14de68cf-2a3f-4a26-ab3f-6cbbde58a29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092014334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.4092014334
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2163419888
Short name T352
Test name
Test status
Simulation time 14762755820 ps
CPU time 34.26 seconds
Started May 19 01:55:56 PM PDT 24
Finished May 19 01:56:37 PM PDT 24
Peak memory 217644 kb
Host smart-2c226136-91e3-4e01-a77d-3c435cdc70d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163419888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2163419888
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2065849374
Short name T661
Test name
Test status
Simulation time 12020105915 ps
CPU time 96.3 seconds
Started May 19 01:56:17 PM PDT 24
Finished May 19 01:57:54 PM PDT 24
Peak memory 223712 kb
Host smart-428c278e-0db6-4f12-9c2e-1fae5dedd7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065849374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2065849374
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_intercept.4124402894
Short name T508
Test name
Test status
Simulation time 72808759 ps
CPU time 2.14 seconds
Started May 19 01:56:05 PM PDT 24
Finished May 19 01:56:09 PM PDT 24
Peak memory 216192 kb
Host smart-769fc266-bd60-4487-b012-2f87bd1b6861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124402894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.4124402894
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1777730305
Short name T299
Test name
Test status
Simulation time 4358029292 ps
CPU time 42.07 seconds
Started May 19 01:56:06 PM PDT 24
Finished May 19 01:56:49 PM PDT 24
Peak memory 237036 kb
Host smart-bfa0d97f-0bbb-4b44-b45c-e4c8008c448f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777730305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1777730305
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.492112146
Short name T956
Test name
Test status
Simulation time 8070935714 ps
CPU time 21.5 seconds
Started May 19 01:56:01 PM PDT 24
Finished May 19 01:56:26 PM PDT 24
Peak memory 219604 kb
Host smart-2850e9aa-a56e-4234-a70e-1f3603616db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492112146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.492112146
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1935342456
Short name T816
Test name
Test status
Simulation time 468882127 ps
CPU time 4.09 seconds
Started May 19 01:56:04 PM PDT 24
Finished May 19 01:56:10 PM PDT 24
Peak memory 233848 kb
Host smart-841d7ea9-0699-4f64-a97e-d4864e97598e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935342456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1935342456
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3802437181
Short name T657
Test name
Test status
Simulation time 1260074056 ps
CPU time 6.68 seconds
Started May 19 01:55:55 PM PDT 24
Finished May 19 01:56:09 PM PDT 24
Peak memory 219184 kb
Host smart-a61b75f5-8449-4444-bc60-43951c029f19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3802437181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3802437181
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2475232543
Short name T627
Test name
Test status
Simulation time 66103563885 ps
CPU time 202.1 seconds
Started May 19 01:55:57 PM PDT 24
Finished May 19 01:59:25 PM PDT 24
Peak memory 232984 kb
Host smart-c2eb669a-4755-43ab-a505-052c33c00f35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475232543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2475232543
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2966064777
Short name T626
Test name
Test status
Simulation time 29401985785 ps
CPU time 35.63 seconds
Started May 19 01:56:10 PM PDT 24
Finished May 19 01:56:46 PM PDT 24
Peak memory 216468 kb
Host smart-a8d4c598-97f2-40d7-ba8a-1cef86df80bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966064777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2966064777
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.103973716
Short name T446
Test name
Test status
Simulation time 1002274952 ps
CPU time 2.89 seconds
Started May 19 01:56:05 PM PDT 24
Finished May 19 01:56:10 PM PDT 24
Peak memory 216396 kb
Host smart-b4a072a6-9703-4b30-a781-84201aca72b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103973716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.103973716
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1114971011
Short name T356
Test name
Test status
Simulation time 120637795 ps
CPU time 1.33 seconds
Started May 19 01:56:04 PM PDT 24
Finished May 19 01:56:07 PM PDT 24
Peak memory 216360 kb
Host smart-37b1eb84-e6e1-4505-866e-41e3638cb84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114971011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1114971011
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1631149424
Short name T63
Test name
Test status
Simulation time 82144164 ps
CPU time 0.97 seconds
Started May 19 01:56:11 PM PDT 24
Finished May 19 01:56:12 PM PDT 24
Peak memory 205800 kb
Host smart-bd23f95e-a4a3-4a58-93c8-a678d4170f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631149424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1631149424
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.397763421
Short name T937
Test name
Test status
Simulation time 244255890 ps
CPU time 2.87 seconds
Started May 19 01:56:00 PM PDT 24
Finished May 19 01:56:07 PM PDT 24
Peak memory 232740 kb
Host smart-6c5553ca-8dbe-4ac8-87b4-c5df0de3124b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397763421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.397763421
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.4131027034
Short name T72
Test name
Test status
Simulation time 17895025 ps
CPU time 0.76 seconds
Started May 19 01:56:17 PM PDT 24
Finished May 19 01:56:19 PM PDT 24
Peak memory 205392 kb
Host smart-a8c3aefb-bbf8-45f3-b0b8-1258182487c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131027034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
4131027034
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2818389557
Short name T449
Test name
Test status
Simulation time 732017184 ps
CPU time 6.7 seconds
Started May 19 01:56:25 PM PDT 24
Finished May 19 01:56:33 PM PDT 24
Peak memory 218836 kb
Host smart-7e2d4d71-02fe-49d6-8ceb-7bc24e3d9ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818389557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2818389557
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.690616202
Short name T616
Test name
Test status
Simulation time 69099352 ps
CPU time 0.79 seconds
Started May 19 01:56:01 PM PDT 24
Finished May 19 01:56:06 PM PDT 24
Peak memory 206436 kb
Host smart-fbda4ca0-fb69-4229-8822-bb671482f129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690616202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.690616202
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3298318530
Short name T207
Test name
Test status
Simulation time 42819619055 ps
CPU time 46.37 seconds
Started May 19 01:56:08 PM PDT 24
Finished May 19 01:56:56 PM PDT 24
Peak memory 240916 kb
Host smart-e4a11a54-bdf5-42b7-9d1a-f1d0cc2f423b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298318530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3298318530
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.195295782
Short name T313
Test name
Test status
Simulation time 18273315420 ps
CPU time 76.64 seconds
Started May 19 01:56:24 PM PDT 24
Finished May 19 01:57:43 PM PDT 24
Peak memory 251456 kb
Host smart-b9b21ac0-4049-4f4a-ad8d-6e5950833aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195295782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.195295782
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.4042421850
Short name T2
Test name
Test status
Simulation time 54118051 ps
CPU time 2.25 seconds
Started May 19 01:56:05 PM PDT 24
Finished May 19 01:56:09 PM PDT 24
Peak memory 224516 kb
Host smart-5c05ddd7-c233-4575-94f7-a4774eb85375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042421850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4042421850
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2947867097
Short name T17
Test name
Test status
Simulation time 446500734 ps
CPU time 4.15 seconds
Started May 19 01:56:03 PM PDT 24
Finished May 19 01:56:09 PM PDT 24
Peak memory 233620 kb
Host smart-82b294e1-181d-4dce-8133-8df106aaf1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947867097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2947867097
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.520673998
Short name T324
Test name
Test status
Simulation time 2608672870 ps
CPU time 26.67 seconds
Started May 19 01:56:29 PM PDT 24
Finished May 19 01:56:56 PM PDT 24
Peak memory 241072 kb
Host smart-7e44ac89-a983-4fdc-a16a-4fe0f061209a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520673998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.520673998
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3307610012
Short name T959
Test name
Test status
Simulation time 385084311 ps
CPU time 3.4 seconds
Started May 19 01:56:18 PM PDT 24
Finished May 19 01:56:23 PM PDT 24
Peak memory 234408 kb
Host smart-5077d0b6-5f02-4c88-821f-83c067722e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307610012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3307610012
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.281885016
Short name T203
Test name
Test status
Simulation time 5315515925 ps
CPU time 5.32 seconds
Started May 19 01:56:01 PM PDT 24
Finished May 19 01:56:10 PM PDT 24
Peak memory 236596 kb
Host smart-a244c8a6-2d05-42bc-9c1c-26ef6dd10254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281885016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.281885016
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3141675134
Short name T954
Test name
Test status
Simulation time 1949885236 ps
CPU time 20.6 seconds
Started May 19 01:56:10 PM PDT 24
Finished May 19 01:56:31 PM PDT 24
Peak memory 222268 kb
Host smart-f2a88b40-0f5d-434d-88f4-02de0f75de5b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3141675134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3141675134
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.4029930948
Short name T603
Test name
Test status
Simulation time 1755693542 ps
CPU time 7.88 seconds
Started May 19 01:56:11 PM PDT 24
Finished May 19 01:56:20 PM PDT 24
Peak memory 216348 kb
Host smart-fc6825a5-6e52-4b3f-8716-79c5bb9b7c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029930948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.4029930948
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.46790902
Short name T380
Test name
Test status
Simulation time 1922351397 ps
CPU time 4.03 seconds
Started May 19 01:56:19 PM PDT 24
Finished May 19 01:56:25 PM PDT 24
Peak memory 216412 kb
Host smart-7965c005-9907-4726-9fcd-dd375bdde69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46790902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.46790902
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1062281716
Short name T898
Test name
Test status
Simulation time 51556315 ps
CPU time 1.38 seconds
Started May 19 01:56:22 PM PDT 24
Finished May 19 01:56:24 PM PDT 24
Peak memory 216436 kb
Host smart-99e4d79b-1f6e-424c-9ef1-f40aafdd2cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062281716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1062281716
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2635949191
Short name T802
Test name
Test status
Simulation time 218102119 ps
CPU time 0.81 seconds
Started May 19 01:55:59 PM PDT 24
Finished May 19 01:56:05 PM PDT 24
Peak memory 206180 kb
Host smart-63cbc7fa-2808-4c89-bd12-132de8e24e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635949191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2635949191
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.4037751116
Short name T897
Test name
Test status
Simulation time 414024805 ps
CPU time 2.74 seconds
Started May 19 01:55:58 PM PDT 24
Finished May 19 01:56:06 PM PDT 24
Peak memory 218684 kb
Host smart-8de65c52-e88e-4fb6-aa48-2f8e12341ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037751116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.4037751116
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4208924636
Short name T669
Test name
Test status
Simulation time 13307670 ps
CPU time 0.71 seconds
Started May 19 01:56:11 PM PDT 24
Finished May 19 01:56:13 PM PDT 24
Peak memory 204748 kb
Host smart-91c1dabb-da76-4d6a-b766-b03c6bf91c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208924636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4208924636
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1914728418
Short name T662
Test name
Test status
Simulation time 3959970482 ps
CPU time 10.89 seconds
Started May 19 01:56:00 PM PDT 24
Finished May 19 01:56:15 PM PDT 24
Peak memory 220048 kb
Host smart-6fee8395-fa43-41be-8a43-702513b500a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914728418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1914728418
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1837012275
Short name T588
Test name
Test status
Simulation time 56916929 ps
CPU time 0.75 seconds
Started May 19 01:56:24 PM PDT 24
Finished May 19 01:56:26 PM PDT 24
Peak memory 205396 kb
Host smart-7af95c6b-c778-4379-aed0-81c89d5ec78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837012275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1837012275
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.224978384
Short name T222
Test name
Test status
Simulation time 49550060178 ps
CPU time 300.62 seconds
Started May 19 01:56:04 PM PDT 24
Finished May 19 02:01:07 PM PDT 24
Peak memory 249300 kb
Host smart-c25efd8f-d12e-4724-b77c-2222bcf33fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224978384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.224978384
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2302532133
Short name T363
Test name
Test status
Simulation time 4534019908 ps
CPU time 53.5 seconds
Started May 19 01:56:19 PM PDT 24
Finished May 19 01:57:14 PM PDT 24
Peak memory 253244 kb
Host smart-12942bb0-e728-49d7-8049-c1e90e495a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302532133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2302532133
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2784441160
Short name T617
Test name
Test status
Simulation time 13587982917 ps
CPU time 92.71 seconds
Started May 19 01:56:04 PM PDT 24
Finished May 19 01:57:39 PM PDT 24
Peak memory 255556 kb
Host smart-dff11d7d-8340-4df1-9477-6965784e6409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784441160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2784441160
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3599994692
Short name T699
Test name
Test status
Simulation time 10234596933 ps
CPU time 40.62 seconds
Started May 19 01:56:03 PM PDT 24
Finished May 19 01:56:46 PM PDT 24
Peak memory 240912 kb
Host smart-68023db0-d9e4-4cb7-a510-4defbd25ecd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599994692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3599994692
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.931587970
Short name T227
Test name
Test status
Simulation time 6530581903 ps
CPU time 18.64 seconds
Started May 19 01:56:19 PM PDT 24
Finished May 19 01:56:39 PM PDT 24
Peak memory 234060 kb
Host smart-73786e49-d72f-42d5-bbb1-f7f5f66eb7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931587970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.931587970
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.652267818
Short name T156
Test name
Test status
Simulation time 738085318 ps
CPU time 12.65 seconds
Started May 19 01:56:05 PM PDT 24
Finished May 19 01:56:19 PM PDT 24
Peak memory 233540 kb
Host smart-3f8358d8-6c68-4eab-a31f-1af425a801dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652267818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.652267818
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.815650511
Short name T265
Test name
Test status
Simulation time 107882771 ps
CPU time 3.29 seconds
Started May 19 01:56:02 PM PDT 24
Finished May 19 01:56:12 PM PDT 24
Peak memory 234876 kb
Host smart-45017dd8-2361-46d0-8c4f-26371c57d93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815650511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.815650511
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2767243329
Short name T14
Test name
Test status
Simulation time 525953912 ps
CPU time 2.77 seconds
Started May 19 01:56:21 PM PDT 24
Finished May 19 01:56:25 PM PDT 24
Peak memory 224524 kb
Host smart-fff1c86a-076c-4f7c-be73-02159d57d441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767243329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2767243329
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1188089307
Short name T604
Test name
Test status
Simulation time 815738645 ps
CPU time 5.26 seconds
Started May 19 01:56:19 PM PDT 24
Finished May 19 01:56:26 PM PDT 24
Peak memory 222864 kb
Host smart-8a081f89-9141-4b3d-a39b-b091ea1f97a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1188089307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1188089307
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.188037968
Short name T103
Test name
Test status
Simulation time 3222995230 ps
CPU time 32.46 seconds
Started May 19 01:56:20 PM PDT 24
Finished May 19 01:56:54 PM PDT 24
Peak memory 235532 kb
Host smart-de24f1ce-785b-4784-9498-6365a1067ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188037968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.188037968
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4134512444
Short name T497
Test name
Test status
Simulation time 9747669976 ps
CPU time 28.8 seconds
Started May 19 01:56:09 PM PDT 24
Finished May 19 01:56:38 PM PDT 24
Peak memory 216564 kb
Host smart-76940741-f292-448d-b33e-645afb77333f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134512444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4134512444
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2371260537
Short name T552
Test name
Test status
Simulation time 3089574620 ps
CPU time 5.03 seconds
Started May 19 01:56:19 PM PDT 24
Finished May 19 01:56:26 PM PDT 24
Peak memory 216492 kb
Host smart-dc5ad749-73c4-46f5-bf59-b80d25d70aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371260537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2371260537
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.701423646
Short name T720
Test name
Test status
Simulation time 166659200 ps
CPU time 0.87 seconds
Started May 19 01:56:04 PM PDT 24
Finished May 19 01:56:07 PM PDT 24
Peak memory 206820 kb
Host smart-4518e3b0-3a02-4841-8d82-f23582b4c36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701423646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.701423646
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3920031366
Short name T649
Test name
Test status
Simulation time 32227544 ps
CPU time 0.83 seconds
Started May 19 01:56:32 PM PDT 24
Finished May 19 01:56:33 PM PDT 24
Peak memory 205696 kb
Host smart-46c05234-cc7f-4422-b0b3-f3cd86526302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920031366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3920031366
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1891343112
Short name T589
Test name
Test status
Simulation time 96575942 ps
CPU time 2.36 seconds
Started May 19 01:56:15 PM PDT 24
Finished May 19 01:56:18 PM PDT 24
Peak memory 218536 kb
Host smart-ddb88eea-9630-44e2-a84d-1ed7308ec1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891343112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1891343112
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3579573872
Short name T600
Test name
Test status
Simulation time 11897862 ps
CPU time 0.7 seconds
Started May 19 01:56:13 PM PDT 24
Finished May 19 01:56:14 PM PDT 24
Peak memory 204728 kb
Host smart-5fd0fd97-194b-464b-8304-fe06d1d1bb86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579573872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3579573872
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.392221517
Short name T595
Test name
Test status
Simulation time 190764614 ps
CPU time 3.09 seconds
Started May 19 01:56:31 PM PDT 24
Finished May 19 01:56:36 PM PDT 24
Peak memory 218816 kb
Host smart-60018051-44d5-4518-a983-f008cc45d3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392221517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.392221517
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2601897298
Short name T650
Test name
Test status
Simulation time 19522614 ps
CPU time 0.79 seconds
Started May 19 01:56:16 PM PDT 24
Finished May 19 01:56:18 PM PDT 24
Peak memory 206448 kb
Host smart-ac0534b6-4016-4e6b-a160-61615307eaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601897298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2601897298
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.154534743
Short name T970
Test name
Test status
Simulation time 16847604312 ps
CPU time 59.34 seconds
Started May 19 01:56:15 PM PDT 24
Finished May 19 01:57:15 PM PDT 24
Peak memory 250712 kb
Host smart-7931b244-3ba7-47f3-827a-4045ba7b529c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154534743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.154534743
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2830201319
Short name T286
Test name
Test status
Simulation time 183454819566 ps
CPU time 428.19 seconds
Started May 19 01:56:25 PM PDT 24
Finished May 19 02:03:35 PM PDT 24
Peak memory 249404 kb
Host smart-3773cfa8-451a-446b-8024-469926a7ea4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830201319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2830201319
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4140773080
Short name T635
Test name
Test status
Simulation time 107661940606 ps
CPU time 244.85 seconds
Started May 19 01:56:26 PM PDT 24
Finished May 19 02:00:32 PM PDT 24
Peak memory 252484 kb
Host smart-6ccd8bf8-3e52-4b0c-a147-e3fa9518c992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140773080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4140773080
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4159181976
Short name T738
Test name
Test status
Simulation time 210448765 ps
CPU time 4.44 seconds
Started May 19 01:56:12 PM PDT 24
Finished May 19 01:56:17 PM PDT 24
Peak memory 224480 kb
Host smart-9719c6ff-0bee-4410-bfcd-d37d1c539364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159181976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4159181976
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3838425958
Short name T326
Test name
Test status
Simulation time 805257029 ps
CPU time 9.02 seconds
Started May 19 01:56:24 PM PDT 24
Finished May 19 01:56:35 PM PDT 24
Peak memory 220740 kb
Host smart-907970a6-04d6-4793-a24e-2f344985e900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838425958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3838425958
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.4062079644
Short name T853
Test name
Test status
Simulation time 1125800584 ps
CPU time 5.78 seconds
Started May 19 01:56:18 PM PDT 24
Finished May 19 01:56:25 PM PDT 24
Peak memory 217880 kb
Host smart-99d26c68-ebfd-4d84-b557-5ced841efb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062079644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4062079644
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3419035823
Short name T159
Test name
Test status
Simulation time 245931981 ps
CPU time 5.16 seconds
Started May 19 01:56:22 PM PDT 24
Finished May 19 01:56:28 PM PDT 24
Peak memory 221164 kb
Host smart-f97c40ec-499b-4d47-a8f7-6551d124c548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419035823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3419035823
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1615243121
Short name T947
Test name
Test status
Simulation time 579670800 ps
CPU time 2.3 seconds
Started May 19 01:56:24 PM PDT 24
Finished May 19 01:56:28 PM PDT 24
Peak memory 216928 kb
Host smart-d058a164-abf4-4ac8-921b-e31a881b2137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615243121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1615243121
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.52596081
Short name T174
Test name
Test status
Simulation time 1113211693 ps
CPU time 16.37 seconds
Started May 19 01:56:19 PM PDT 24
Finished May 19 01:56:37 PM PDT 24
Peak memory 220732 kb
Host smart-934cd2ce-1e14-4335-8304-eea30c4392bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=52596081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direc
t.52596081
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2106610817
Short name T258
Test name
Test status
Simulation time 13243529594 ps
CPU time 143.48 seconds
Started May 19 01:56:15 PM PDT 24
Finished May 19 01:58:40 PM PDT 24
Peak memory 254956 kb
Host smart-21ded64c-6e61-4edc-8ffb-229da642dc2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106610817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2106610817
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1612020220
Short name T498
Test name
Test status
Simulation time 7749950625 ps
CPU time 16.8 seconds
Started May 19 01:56:21 PM PDT 24
Finished May 19 01:56:39 PM PDT 24
Peak memory 216588 kb
Host smart-46d5f6e2-abe0-4791-9dad-0afa325203fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612020220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1612020220
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.4152424695
Short name T472
Test name
Test status
Simulation time 4145825011 ps
CPU time 7.63 seconds
Started May 19 01:56:15 PM PDT 24
Finished May 19 01:56:24 PM PDT 24
Peak memory 216540 kb
Host smart-7f07a4f9-96c4-43e3-81b8-ff5a4b50be1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152424695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.4152424695
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2848911919
Short name T900
Test name
Test status
Simulation time 440900795 ps
CPU time 2.28 seconds
Started May 19 01:56:21 PM PDT 24
Finished May 19 01:56:24 PM PDT 24
Peak memory 216364 kb
Host smart-859449c3-58b5-4064-a9c2-3e15279c3ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848911919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2848911919
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.320927039
Short name T87
Test name
Test status
Simulation time 55706919 ps
CPU time 0.82 seconds
Started May 19 01:56:22 PM PDT 24
Finished May 19 01:56:23 PM PDT 24
Peak memory 205848 kb
Host smart-651789f7-c90d-4042-b1ee-81896e957345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320927039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.320927039
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2657831582
Short name T904
Test name
Test status
Simulation time 589654893 ps
CPU time 2.74 seconds
Started May 19 01:56:16 PM PDT 24
Finished May 19 01:56:20 PM PDT 24
Peak memory 216348 kb
Host smart-188fbd6f-a88c-49b9-8e7b-f793ece12b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657831582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2657831582
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1836438528
Short name T881
Test name
Test status
Simulation time 23066802 ps
CPU time 0.72 seconds
Started May 19 01:56:20 PM PDT 24
Finished May 19 01:56:22 PM PDT 24
Peak memory 205676 kb
Host smart-1b8f0cfa-5d94-4809-9aa3-844e5c2b690d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836438528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1836438528
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.4094764292
Short name T325
Test name
Test status
Simulation time 39104916 ps
CPU time 2.54 seconds
Started May 19 01:56:14 PM PDT 24
Finished May 19 01:56:18 PM PDT 24
Peak memory 234252 kb
Host smart-e67a324d-7afd-475f-83fd-c6d5c56d756d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094764292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.4094764292
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.267081899
Short name T975
Test name
Test status
Simulation time 114997476 ps
CPU time 0.73 seconds
Started May 19 01:56:23 PM PDT 24
Finished May 19 01:56:25 PM PDT 24
Peak memory 206400 kb
Host smart-df4de0a8-cfc8-46f0-9ea0-32bfc8a4b760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267081899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.267081899
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4221573181
Short name T279
Test name
Test status
Simulation time 37153887253 ps
CPU time 310.09 seconds
Started May 19 01:56:24 PM PDT 24
Finished May 19 02:01:36 PM PDT 24
Peak memory 253116 kb
Host smart-37fde6cf-eb6a-4152-bd33-7e323579c0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221573181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4221573181
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3412764519
Short name T241
Test name
Test status
Simulation time 70299683020 ps
CPU time 160.39 seconds
Started May 19 01:56:32 PM PDT 24
Finished May 19 01:59:13 PM PDT 24
Peak memory 252668 kb
Host smart-b99c8ea2-3dfc-464c-a8a9-4827aa48b2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412764519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3412764519
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.433058597
Short name T187
Test name
Test status
Simulation time 5526677955 ps
CPU time 22.4 seconds
Started May 19 01:56:18 PM PDT 24
Finished May 19 01:56:42 PM PDT 24
Peak memory 241080 kb
Host smart-37518687-fa28-4a67-8b09-16edb6a21aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433058597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.433058597
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1741924151
Short name T349
Test name
Test status
Simulation time 910014064 ps
CPU time 7.65 seconds
Started May 19 01:56:18 PM PDT 24
Finished May 19 01:56:27 PM PDT 24
Peak memory 224752 kb
Host smart-0899263a-dd20-43a4-817e-3b0aca89fc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741924151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1741924151
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2181585203
Short name T323
Test name
Test status
Simulation time 4447410669 ps
CPU time 8.92 seconds
Started May 19 01:56:16 PM PDT 24
Finished May 19 01:56:26 PM PDT 24
Peak memory 219024 kb
Host smart-46da8ab0-dc61-4f8a-9381-c190685eeb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181585203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2181585203
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1060965852
Short name T204
Test name
Test status
Simulation time 20809521118 ps
CPU time 93.09 seconds
Started May 19 01:56:15 PM PDT 24
Finished May 19 01:57:48 PM PDT 24
Peak memory 229780 kb
Host smart-2d851c3a-c812-4a71-a580-4b2afc24939d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060965852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1060965852
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.4000322324
Short name T606
Test name
Test status
Simulation time 12997649843 ps
CPU time 11.56 seconds
Started May 19 01:56:19 PM PDT 24
Finished May 19 01:56:32 PM PDT 24
Peak memory 224672 kb
Host smart-f27db3af-8604-47a8-9d1a-9b4e5f86fe35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000322324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.4000322324
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1390315776
Short name T490
Test name
Test status
Simulation time 574749432 ps
CPU time 6.5 seconds
Started May 19 01:56:23 PM PDT 24
Finished May 19 01:56:30 PM PDT 24
Peak memory 233508 kb
Host smart-e1952db0-a1f7-4607-8720-f2e462eedd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390315776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1390315776
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.961714961
Short name T917
Test name
Test status
Simulation time 177166188 ps
CPU time 3.99 seconds
Started May 19 01:56:09 PM PDT 24
Finished May 19 01:56:14 PM PDT 24
Peak memory 222900 kb
Host smart-e24e8c38-d6a8-4faf-9868-5af6fd8cdb1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=961714961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.961714961
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.871760711
Short name T180
Test name
Test status
Simulation time 78385647 ps
CPU time 1.11 seconds
Started May 19 01:56:05 PM PDT 24
Finished May 19 01:56:08 PM PDT 24
Peak memory 207728 kb
Host smart-bdbf4076-7bdb-4753-80fe-c556786df631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871760711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.871760711
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1707090878
Short name T742
Test name
Test status
Simulation time 308752858 ps
CPU time 3.9 seconds
Started May 19 01:56:08 PM PDT 24
Finished May 19 01:56:13 PM PDT 24
Peak memory 216632 kb
Host smart-5f7ec862-c33a-4984-9b24-6d585186df82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707090878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1707090878
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.655144326
Short name T788
Test name
Test status
Simulation time 19013959998 ps
CPU time 7.71 seconds
Started May 19 01:56:07 PM PDT 24
Finished May 19 01:56:15 PM PDT 24
Peak memory 216788 kb
Host smart-a4f843c2-3699-4295-8191-baa5a708514e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655144326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.655144326
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.4286466413
Short name T857
Test name
Test status
Simulation time 30869716 ps
CPU time 1.01 seconds
Started May 19 01:56:18 PM PDT 24
Finished May 19 01:56:20 PM PDT 24
Peak memory 207052 kb
Host smart-625855dd-6817-4332-a319-b2e8847462e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286466413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.4286466413
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1755663326
Short name T1
Test name
Test status
Simulation time 68861341 ps
CPU time 0.8 seconds
Started May 19 01:56:25 PM PDT 24
Finished May 19 01:56:27 PM PDT 24
Peak memory 205844 kb
Host smart-a4a48ef0-d1a5-4ece-987b-6beff25b7442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755663326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1755663326
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2144733537
Short name T723
Test name
Test status
Simulation time 10278030576 ps
CPU time 19.31 seconds
Started May 19 01:56:22 PM PDT 24
Finished May 19 01:56:42 PM PDT 24
Peak memory 232936 kb
Host smart-9f4e4b23-e815-4d33-ad84-33d628c0a994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144733537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2144733537
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1929598026
Short name T460
Test name
Test status
Simulation time 188113436 ps
CPU time 0.69 seconds
Started May 19 01:56:19 PM PDT 24
Finished May 19 01:56:22 PM PDT 24
Peak memory 204732 kb
Host smart-5cad16b3-1961-4147-9aa9-19b1b373c4bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929598026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1929598026
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2024520948
Short name T516
Test name
Test status
Simulation time 76619621 ps
CPU time 2.11 seconds
Started May 19 01:56:30 PM PDT 24
Finished May 19 01:56:33 PM PDT 24
Peak memory 218544 kb
Host smart-b83e8109-4c32-4c75-88c7-669b02d47c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024520948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2024520948
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3842705134
Short name T522
Test name
Test status
Simulation time 38921468 ps
CPU time 0.74 seconds
Started May 19 01:56:17 PM PDT 24
Finished May 19 01:56:18 PM PDT 24
Peak memory 206476 kb
Host smart-b67dba4d-ce08-47ef-ace8-c168d416f819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842705134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3842705134
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1488416443
Short name T692
Test name
Test status
Simulation time 896089767 ps
CPU time 7.94 seconds
Started May 19 01:56:35 PM PDT 24
Finished May 19 01:56:44 PM PDT 24
Peak memory 236244 kb
Host smart-ae590fd3-1af7-4d77-b014-07ba67c60546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488416443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1488416443
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1774033607
Short name T185
Test name
Test status
Simulation time 45562664810 ps
CPU time 436.81 seconds
Started May 19 01:56:25 PM PDT 24
Finished May 19 02:03:43 PM PDT 24
Peak memory 256132 kb
Host smart-9b794c52-084a-4534-882a-6259582c8025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774033607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1774033607
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3087543611
Short name T348
Test name
Test status
Simulation time 24588081559 ps
CPU time 68.02 seconds
Started May 19 01:56:26 PM PDT 24
Finished May 19 01:57:35 PM PDT 24
Peak memory 257428 kb
Host smart-47b81da3-430d-4659-8b63-64ffa8d341a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087543611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3087543611
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1255900547
Short name T295
Test name
Test status
Simulation time 7999718613 ps
CPU time 37.2 seconds
Started May 19 01:56:18 PM PDT 24
Finished May 19 01:56:57 PM PDT 24
Peak memory 234268 kb
Host smart-9a7c9b2e-591d-495e-af0c-7b9f60e82fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255900547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1255900547
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.355471590
Short name T854
Test name
Test status
Simulation time 289215852 ps
CPU time 5.57 seconds
Started May 19 01:56:19 PM PDT 24
Finished May 19 01:56:26 PM PDT 24
Peak memory 218460 kb
Host smart-dfde2eb5-bf99-4ceb-8251-9c1cfcde57ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355471590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.355471590
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2606723410
Short name T337
Test name
Test status
Simulation time 188444541 ps
CPU time 2.37 seconds
Started May 19 01:56:13 PM PDT 24
Finished May 19 01:56:16 PM PDT 24
Peak memory 224476 kb
Host smart-66c6ac66-fbdf-4d60-b238-c0a70f343175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606723410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2606723410
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1217529418
Short name T652
Test name
Test status
Simulation time 787500075 ps
CPU time 4.89 seconds
Started May 19 01:56:15 PM PDT 24
Finished May 19 01:56:20 PM PDT 24
Peak memory 218652 kb
Host smart-c64acb13-5e2e-4f1e-ad0c-652ccf3e86a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217529418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1217529418
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1853245623
Short name T400
Test name
Test status
Simulation time 542038806 ps
CPU time 6.68 seconds
Started May 19 01:56:12 PM PDT 24
Finished May 19 01:56:20 PM PDT 24
Peak memory 218940 kb
Host smart-c7a8a1ee-e2db-4e7e-9455-b2d063b37476
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1853245623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1853245623
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1043500519
Short name T99
Test name
Test status
Simulation time 20336211094 ps
CPU time 192.77 seconds
Started May 19 01:56:33 PM PDT 24
Finished May 19 01:59:47 PM PDT 24
Peak memory 249604 kb
Host smart-1ed70295-577b-4b27-bde0-d99213c13cce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043500519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1043500519
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.318381691
Short name T492
Test name
Test status
Simulation time 8535886692 ps
CPU time 20.82 seconds
Started May 19 01:56:13 PM PDT 24
Finished May 19 01:56:35 PM PDT 24
Peak memory 217044 kb
Host smart-ea2ba9d2-a5f2-4ce2-bae2-c647ea0836b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318381691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.318381691
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2031395858
Short name T563
Test name
Test status
Simulation time 29714969 ps
CPU time 0.68 seconds
Started May 19 01:56:27 PM PDT 24
Finished May 19 01:56:29 PM PDT 24
Peak memory 205576 kb
Host smart-674a3f91-f062-4409-874b-e37943de61b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031395858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2031395858
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3267906492
Short name T605
Test name
Test status
Simulation time 190515162 ps
CPU time 0.84 seconds
Started May 19 01:56:11 PM PDT 24
Finished May 19 01:56:12 PM PDT 24
Peak memory 205840 kb
Host smart-e8eab42f-a7be-43a8-9e5f-0eb41e75a671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267906492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3267906492
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.953132078
Short name T411
Test name
Test status
Simulation time 20439422 ps
CPU time 0.77 seconds
Started May 19 01:56:19 PM PDT 24
Finished May 19 01:56:21 PM PDT 24
Peak memory 205856 kb
Host smart-a66c884d-4626-4ca6-8ab1-35a0f06aefda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953132078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.953132078
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1944125786
Short name T473
Test name
Test status
Simulation time 238970630 ps
CPU time 3.69 seconds
Started May 19 01:56:31 PM PDT 24
Finished May 19 01:56:35 PM PDT 24
Peak memory 234880 kb
Host smart-ea8f6682-7352-4880-ad3c-b9574e9f3dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944125786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1944125786
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3506139581
Short name T856
Test name
Test status
Simulation time 142191375 ps
CPU time 0.69 seconds
Started May 19 01:56:25 PM PDT 24
Finished May 19 01:56:27 PM PDT 24
Peak memory 205372 kb
Host smart-ac5bbe23-a2c7-4723-be65-77bf1e32dcf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506139581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3506139581
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.972047106
Short name T684
Test name
Test status
Simulation time 1728371576 ps
CPU time 10.78 seconds
Started May 19 01:56:40 PM PDT 24
Finished May 19 01:56:57 PM PDT 24
Peak memory 234356 kb
Host smart-6e2c2cf1-ab6c-4328-8686-21a94eb5e560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972047106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.972047106
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.190912740
Short name T391
Test name
Test status
Simulation time 62526854 ps
CPU time 0.76 seconds
Started May 19 01:56:18 PM PDT 24
Finished May 19 01:56:19 PM PDT 24
Peak memory 206464 kb
Host smart-0520f203-ef9e-4737-8a3e-8c2dd5353ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190912740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.190912740
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2084054558
Short name T255
Test name
Test status
Simulation time 59730257380 ps
CPU time 128.39 seconds
Started May 19 01:56:38 PM PDT 24
Finished May 19 01:58:51 PM PDT 24
Peak memory 256420 kb
Host smart-eed4fead-e4aa-4f29-9729-9aa8622c6ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084054558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2084054558
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.374001680
Short name T191
Test name
Test status
Simulation time 2421567833 ps
CPU time 25.92 seconds
Started May 19 01:56:30 PM PDT 24
Finished May 19 01:56:57 PM PDT 24
Peak memory 241132 kb
Host smart-9d231966-27e6-4e00-8ca0-6d31a5cab966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374001680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.374001680
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1339574068
Short name T557
Test name
Test status
Simulation time 1017647462 ps
CPU time 18.67 seconds
Started May 19 01:56:31 PM PDT 24
Finished May 19 01:56:51 PM PDT 24
Peak memory 232772 kb
Host smart-dae04242-f9f8-45a8-8ad8-989b7283e228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339574068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1339574068
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3797064657
Short name T908
Test name
Test status
Simulation time 11573194594 ps
CPU time 11.7 seconds
Started May 19 01:56:19 PM PDT 24
Finished May 19 01:56:32 PM PDT 24
Peak memory 234508 kb
Host smart-0bdd6947-edea-4464-a775-9a11ce26a03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797064657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3797064657
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1108388815
Short name T532
Test name
Test status
Simulation time 13000609086 ps
CPU time 28.2 seconds
Started May 19 01:56:27 PM PDT 24
Finished May 19 01:56:56 PM PDT 24
Peak memory 224528 kb
Host smart-980165a1-8f14-4b20-9b9f-0560693f3593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108388815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1108388815
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2827127622
Short name T731
Test name
Test status
Simulation time 31087719 ps
CPU time 2.47 seconds
Started May 19 01:56:30 PM PDT 24
Finished May 19 01:56:34 PM PDT 24
Peak memory 221292 kb
Host smart-4238c72c-12c7-42a0-bb04-e681d8a044fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827127622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2827127622
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.836899011
Short name T950
Test name
Test status
Simulation time 1592781265 ps
CPU time 2.89 seconds
Started May 19 01:56:12 PM PDT 24
Finished May 19 01:56:16 PM PDT 24
Peak memory 218948 kb
Host smart-6379de64-9f65-4eb5-b777-2459cb3fb39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836899011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.836899011
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.913139795
Short name T823
Test name
Test status
Simulation time 1593583088 ps
CPU time 19.19 seconds
Started May 19 01:56:18 PM PDT 24
Finished May 19 01:56:38 PM PDT 24
Peak memory 221612 kb
Host smart-8ea9c2f7-7415-4fa5-908f-ec8915c38472
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=913139795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.913139795
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.960188417
Short name T181
Test name
Test status
Simulation time 98201503 ps
CPU time 0.95 seconds
Started May 19 01:56:24 PM PDT 24
Finished May 19 01:56:26 PM PDT 24
Peak memory 207984 kb
Host smart-96f94585-2f57-4243-b143-17d4e7080777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960188417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.960188417
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3101899435
Short name T355
Test name
Test status
Simulation time 32790613938 ps
CPU time 28.34 seconds
Started May 19 01:56:31 PM PDT 24
Finished May 19 01:57:01 PM PDT 24
Peak memory 220292 kb
Host smart-dbd40793-119e-4e02-8861-045cd3563d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101899435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3101899435
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3347587993
Short name T431
Test name
Test status
Simulation time 26610521389 ps
CPU time 17.6 seconds
Started May 19 01:56:22 PM PDT 24
Finished May 19 01:56:41 PM PDT 24
Peak memory 216488 kb
Host smart-4492cc77-3555-4d6b-b8bd-183ec9c4caae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347587993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3347587993
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1784970051
Short name T805
Test name
Test status
Simulation time 59815354 ps
CPU time 1.43 seconds
Started May 19 01:56:20 PM PDT 24
Finished May 19 01:56:23 PM PDT 24
Peak memory 216452 kb
Host smart-60b5a1f6-e67f-435f-97fc-e21bd00e8eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784970051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1784970051
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.725903219
Short name T777
Test name
Test status
Simulation time 114777444 ps
CPU time 0.85 seconds
Started May 19 01:56:21 PM PDT 24
Finished May 19 01:56:23 PM PDT 24
Peak memory 205816 kb
Host smart-53d04afd-dc54-49af-b799-daabd1b87d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725903219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.725903219
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1658832019
Short name T737
Test name
Test status
Simulation time 3440739684 ps
CPU time 13.13 seconds
Started May 19 01:56:13 PM PDT 24
Finished May 19 01:56:27 PM PDT 24
Peak memory 221436 kb
Host smart-9c6f48da-85a4-4cdb-afa1-95f586641c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658832019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1658832019
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2459878931
Short name T525
Test name
Test status
Simulation time 24315119 ps
CPU time 0.7 seconds
Started May 19 01:54:55 PM PDT 24
Finished May 19 01:55:03 PM PDT 24
Peak memory 204788 kb
Host smart-036e2208-1b8b-45c9-a075-f515186c3380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459878931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
459878931
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.4246705336
Short name T620
Test name
Test status
Simulation time 2442144250 ps
CPU time 12.72 seconds
Started May 19 01:54:50 PM PDT 24
Finished May 19 01:55:10 PM PDT 24
Peak memory 233260 kb
Host smart-26ff355e-0706-4c69-a835-472e34ed1a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246705336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4246705336
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3468167678
Short name T882
Test name
Test status
Simulation time 37869306 ps
CPU time 0.79 seconds
Started May 19 01:54:48 PM PDT 24
Finished May 19 01:54:53 PM PDT 24
Peak memory 206808 kb
Host smart-2ec1f17b-f3bf-4570-9e79-a494265abed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468167678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3468167678
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2995819017
Short name T513
Test name
Test status
Simulation time 1605708265 ps
CPU time 26.97 seconds
Started May 19 01:54:55 PM PDT 24
Finished May 19 01:55:30 PM PDT 24
Peak memory 224544 kb
Host smart-b03596f2-2046-4abf-9424-b4e41534f027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995819017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2995819017
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1474407987
Short name T317
Test name
Test status
Simulation time 79276629848 ps
CPU time 400.06 seconds
Started May 19 01:54:34 PM PDT 24
Finished May 19 02:01:15 PM PDT 24
Peak memory 254396 kb
Host smart-2d492de6-3bda-435e-a38d-61393a29048b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474407987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1474407987
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1183183104
Short name T851
Test name
Test status
Simulation time 3977217073 ps
CPU time 74.71 seconds
Started May 19 01:54:56 PM PDT 24
Finished May 19 01:56:18 PM PDT 24
Peak memory 249404 kb
Host smart-8613e19f-33f7-4e09-8bcf-c08a9b39aa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183183104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1183183104
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3672903514
Short name T347
Test name
Test status
Simulation time 140853516 ps
CPU time 7.67 seconds
Started May 19 01:54:47 PM PDT 24
Finished May 19 01:54:59 PM PDT 24
Peak memory 232700 kb
Host smart-00ff0c7d-812b-45ed-a94a-06d072f1cf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672903514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3672903514
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2036153060
Short name T310
Test name
Test status
Simulation time 5761235028 ps
CPU time 13.24 seconds
Started May 19 01:54:38 PM PDT 24
Finished May 19 01:54:52 PM PDT 24
Peak memory 234128 kb
Host smart-2bcdb610-3baf-484d-9d31-116a0d6afe57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036153060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2036153060
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.18552234
Short name T9
Test name
Test status
Simulation time 16999089741 ps
CPU time 43.65 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:45 PM PDT 24
Peak memory 229800 kb
Host smart-b1189320-75f0-4a75-a310-8f884410f3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18552234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.18552234
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.238857419
Short name T951
Test name
Test status
Simulation time 27188542 ps
CPU time 1.09 seconds
Started May 19 01:54:48 PM PDT 24
Finished May 19 01:54:54 PM PDT 24
Peak memory 216736 kb
Host smart-e950e977-d290-4e85-b784-d21f5532daf3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238857419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.238857419
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3113063107
Short name T208
Test name
Test status
Simulation time 433177824 ps
CPU time 5.84 seconds
Started May 19 01:54:50 PM PDT 24
Finished May 19 01:55:02 PM PDT 24
Peak memory 224524 kb
Host smart-62c347a2-7359-4750-8d5b-8447de2e9e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113063107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3113063107
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.245416932
Short name T928
Test name
Test status
Simulation time 11887216685 ps
CPU time 12.53 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:13 PM PDT 24
Peak memory 229700 kb
Host smart-604bc832-41e8-44bb-8cac-7d1f5531346f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245416932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.245416932
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.4210069758
Short name T539
Test name
Test status
Simulation time 1227314511 ps
CPU time 3.88 seconds
Started May 19 01:54:47 PM PDT 24
Finished May 19 01:54:55 PM PDT 24
Peak memory 219272 kb
Host smart-3af90204-a4dc-4cda-a95c-4b38d2e75cfa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4210069758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.4210069758
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3125618656
Short name T487
Test name
Test status
Simulation time 79925371458 ps
CPU time 183.6 seconds
Started May 19 01:54:35 PM PDT 24
Finished May 19 01:57:40 PM PDT 24
Peak memory 251488 kb
Host smart-22ed9a41-7f9c-464c-acad-e546237682bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125618656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3125618656
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1820795869
Short name T895
Test name
Test status
Simulation time 9501770386 ps
CPU time 12.83 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:14 PM PDT 24
Peak memory 216512 kb
Host smart-7d0bceb3-5190-4479-8ffa-911804d3026e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820795869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1820795869
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3693871642
Short name T818
Test name
Test status
Simulation time 36219870884 ps
CPU time 19.25 seconds
Started May 19 01:54:54 PM PDT 24
Finished May 19 01:55:22 PM PDT 24
Peak memory 216512 kb
Host smart-42d355c4-6633-4ac6-99d2-b8fffb2a559d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693871642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3693871642
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2697952782
Short name T712
Test name
Test status
Simulation time 111587375 ps
CPU time 0.78 seconds
Started May 19 01:54:41 PM PDT 24
Finished May 19 01:54:42 PM PDT 24
Peak memory 205820 kb
Host smart-35bbdc52-51c9-406c-b78b-ae0cfef1ba49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697952782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2697952782
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3154405681
Short name T58
Test name
Test status
Simulation time 31562797 ps
CPU time 0.75 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:02 PM PDT 24
Peak memory 205788 kb
Host smart-a7fd3ec7-4c94-489a-becb-4def0c796fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154405681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3154405681
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2366189521
Short name T542
Test name
Test status
Simulation time 7514900809 ps
CPU time 18.89 seconds
Started May 19 01:54:38 PM PDT 24
Finished May 19 01:54:58 PM PDT 24
Peak memory 229912 kb
Host smart-1bf0f863-2ec1-4b4f-9bd9-f4c8eca6bdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366189521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2366189521
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1962375506
Short name T704
Test name
Test status
Simulation time 12519634 ps
CPU time 0.71 seconds
Started May 19 01:54:50 PM PDT 24
Finished May 19 01:54:58 PM PDT 24
Peak memory 205380 kb
Host smart-f2d7a890-d92f-43dd-850e-c99cd7d77d77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962375506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
962375506
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1300735974
Short name T831
Test name
Test status
Simulation time 270059026 ps
CPU time 3.68 seconds
Started May 19 01:54:48 PM PDT 24
Finished May 19 01:54:57 PM PDT 24
Peak memory 234520 kb
Host smart-da884a7c-9801-41b4-b739-7ede1cb729b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300735974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1300735974
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.222209420
Short name T404
Test name
Test status
Simulation time 36182271 ps
CPU time 0.72 seconds
Started May 19 01:54:48 PM PDT 24
Finished May 19 01:54:53 PM PDT 24
Peak memory 205428 kb
Host smart-82690418-be07-42ae-98ca-9c542f6a8701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222209420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.222209420
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1382264741
Short name T28
Test name
Test status
Simulation time 1923799307 ps
CPU time 31.71 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:55:26 PM PDT 24
Peak memory 240952 kb
Host smart-b21a13ab-d5b8-40d3-9646-76cfa35d8635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382264741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1382264741
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1205990220
Short name T561
Test name
Test status
Simulation time 125581750267 ps
CPU time 232.45 seconds
Started May 19 01:54:47 PM PDT 24
Finished May 19 01:58:44 PM PDT 24
Peak memory 251360 kb
Host smart-bc18d843-59b8-4dde-87c8-e44ee0a15652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205990220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1205990220
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.267435777
Short name T706
Test name
Test status
Simulation time 5718949376 ps
CPU time 72.31 seconds
Started May 19 01:54:45 PM PDT 24
Finished May 19 01:56:07 PM PDT 24
Peak memory 264984 kb
Host smart-c5c65650-b056-44ef-a3db-4afe8b192341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267435777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
267435777
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.711386726
Short name T812
Test name
Test status
Simulation time 109034528 ps
CPU time 4.4 seconds
Started May 19 01:54:50 PM PDT 24
Finished May 19 01:55:01 PM PDT 24
Peak memory 224528 kb
Host smart-c52e4fde-7be8-4a2c-9c71-a38a716eb051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711386726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.711386726
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1674360818
Short name T74
Test name
Test status
Simulation time 241154997 ps
CPU time 4.11 seconds
Started May 19 01:54:35 PM PDT 24
Finished May 19 01:54:40 PM PDT 24
Peak memory 237620 kb
Host smart-82447339-ca9e-4191-91fb-29b2dfff42a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674360818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1674360818
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.648118074
Short name T302
Test name
Test status
Simulation time 49428046634 ps
CPU time 65.37 seconds
Started May 19 01:54:44 PM PDT 24
Finished May 19 01:55:52 PM PDT 24
Peak memory 234788 kb
Host smart-9a8a1ecd-88d6-4846-9eeb-2e528c42017f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648118074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.648118074
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1701279766
Short name T478
Test name
Test status
Simulation time 16997530 ps
CPU time 1.06 seconds
Started May 19 01:54:37 PM PDT 24
Finished May 19 01:54:39 PM PDT 24
Peak memory 216764 kb
Host smart-711b69cf-4575-455f-933f-23b5174ef5eb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701279766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1701279766
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.605417512
Short name T239
Test name
Test status
Simulation time 2848822670 ps
CPU time 7.96 seconds
Started May 19 01:55:07 PM PDT 24
Finished May 19 01:55:18 PM PDT 24
Peak memory 240980 kb
Host smart-932bf9c0-9b2e-4373-8efe-e909e7973c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605417512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
605417512
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3824004134
Short name T608
Test name
Test status
Simulation time 462075932 ps
CPU time 8.35 seconds
Started May 19 01:54:35 PM PDT 24
Finished May 19 01:54:45 PM PDT 24
Peak memory 236336 kb
Host smart-80738f5b-a99b-4151-88e8-905ad95a5b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824004134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3824004134
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.405315872
Short name T496
Test name
Test status
Simulation time 338033965 ps
CPU time 6.32 seconds
Started May 19 01:54:44 PM PDT 24
Finished May 19 01:54:54 PM PDT 24
Peak memory 219112 kb
Host smart-8570b3e6-4cba-412c-b117-1a424fdd633b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=405315872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.405315872
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.4127149749
Short name T949
Test name
Test status
Simulation time 19756608417 ps
CPU time 206.09 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:58:21 PM PDT 24
Peak memory 249528 kb
Host smart-c3ce5630-97b5-46f7-8327-456b271d1e07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127149749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.4127149749
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.818113684
Short name T733
Test name
Test status
Simulation time 1038527721 ps
CPU time 16.49 seconds
Started May 19 01:55:16 PM PDT 24
Finished May 19 01:55:35 PM PDT 24
Peak memory 216456 kb
Host smart-e4223b97-cdbb-4191-8ea3-74356bce490c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818113684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.818113684
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2069430861
Short name T981
Test name
Test status
Simulation time 2098363113 ps
CPU time 3.72 seconds
Started May 19 01:54:58 PM PDT 24
Finished May 19 01:55:09 PM PDT 24
Peak memory 216356 kb
Host smart-8656b559-cd0c-4de7-8e8e-00c83b2b1842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069430861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2069430861
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.679715899
Short name T837
Test name
Test status
Simulation time 15085651 ps
CPU time 0.74 seconds
Started May 19 01:54:47 PM PDT 24
Finished May 19 01:54:51 PM PDT 24
Peak memory 205852 kb
Host smart-48dcb691-5d71-415e-be9b-331c0c148e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679715899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.679715899
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1297348493
Short name T732
Test name
Test status
Simulation time 67373147 ps
CPU time 0.9 seconds
Started May 19 01:54:50 PM PDT 24
Finished May 19 01:54:57 PM PDT 24
Peak memory 205836 kb
Host smart-cf73342e-77d6-4342-abb3-49fdac29fd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297348493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1297348493
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.722072866
Short name T296
Test name
Test status
Simulation time 5026841939 ps
CPU time 11.7 seconds
Started May 19 01:54:42 PM PDT 24
Finished May 19 01:54:54 PM PDT 24
Peak memory 224580 kb
Host smart-ce829ff8-89db-4aea-b4c0-19914c30839d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722072866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.722072866
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2227835565
Short name T436
Test name
Test status
Simulation time 24830534 ps
CPU time 0.75 seconds
Started May 19 01:54:47 PM PDT 24
Finished May 19 01:54:52 PM PDT 24
Peak memory 205396 kb
Host smart-01919f4b-b93c-411a-977a-acd7e8fccc5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227835565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
227835565
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2084484175
Short name T49
Test name
Test status
Simulation time 699702706 ps
CPU time 9.01 seconds
Started May 19 01:54:46 PM PDT 24
Finished May 19 01:54:59 PM PDT 24
Peak memory 218584 kb
Host smart-1c1f553e-79c5-46f6-81e6-6249eee0112c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084484175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2084484175
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1470232994
Short name T447
Test name
Test status
Simulation time 14188855 ps
CPU time 0.73 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:54:55 PM PDT 24
Peak memory 205440 kb
Host smart-21c6a41b-3d63-414f-9915-63056c60ce4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470232994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1470232994
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.111475789
Short name T896
Test name
Test status
Simulation time 14911407137 ps
CPU time 58.17 seconds
Started May 19 01:55:06 PM PDT 24
Finished May 19 01:56:07 PM PDT 24
Peak memory 241096 kb
Host smart-a10cd0ec-2686-4d91-802a-39fc05974bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111475789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.111475789
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.11640637
Short name T163
Test name
Test status
Simulation time 4912237759 ps
CPU time 76.99 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:56:16 PM PDT 24
Peak memory 249464 kb
Host smart-c4bf65c7-f3d2-493d-8902-47d0dc861878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11640637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.11640637
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2165351267
Short name T346
Test name
Test status
Simulation time 2354847629 ps
CPU time 16 seconds
Started May 19 01:55:09 PM PDT 24
Finished May 19 01:55:27 PM PDT 24
Peak memory 241124 kb
Host smart-0db34f03-644c-470c-aab8-57e26bf0112d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165351267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2165351267
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.728178757
Short name T409
Test name
Test status
Simulation time 736103089 ps
CPU time 6.25 seconds
Started May 19 01:54:47 PM PDT 24
Finished May 19 01:54:56 PM PDT 24
Peak memory 233784 kb
Host smart-b7fcb5e9-c5b9-45ce-90ff-a88a98943e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728178757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.728178757
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1520451189
Short name T976
Test name
Test status
Simulation time 7828091675 ps
CPU time 64.28 seconds
Started May 19 01:54:34 PM PDT 24
Finished May 19 01:55:40 PM PDT 24
Peak memory 247524 kb
Host smart-cc513759-85fb-43b4-a9ff-5c6e9a1a6c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520451189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1520451189
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2030760284
Short name T659
Test name
Test status
Simulation time 29134869 ps
CPU time 1.08 seconds
Started May 19 01:54:43 PM PDT 24
Finished May 19 01:54:46 PM PDT 24
Peak memory 216748 kb
Host smart-8060458e-8109-4f65-add6-943e6a792c2c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030760284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2030760284
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2615651164
Short name T320
Test name
Test status
Simulation time 2136665796 ps
CPU time 5.67 seconds
Started May 19 01:54:37 PM PDT 24
Finished May 19 01:54:44 PM PDT 24
Peak memory 233688 kb
Host smart-7c367ff7-c21b-4191-a2ac-87bf4d7db760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615651164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2615651164
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3900616250
Short name T213
Test name
Test status
Simulation time 4626650543 ps
CPU time 9.16 seconds
Started May 19 01:54:39 PM PDT 24
Finished May 19 01:54:49 PM PDT 24
Peak memory 239940 kb
Host smart-93405159-b1d2-45e5-87c0-795202d0a17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900616250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3900616250
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1573820496
Short name T885
Test name
Test status
Simulation time 1271834269 ps
CPU time 8.66 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:10 PM PDT 24
Peak memory 219372 kb
Host smart-a225b3ea-9ac8-4498-888e-3b1ed574c2a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1573820496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1573820496
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.4234146189
Short name T934
Test name
Test status
Simulation time 9681548309 ps
CPU time 35.81 seconds
Started May 19 01:54:59 PM PDT 24
Finished May 19 01:55:41 PM PDT 24
Peak memory 236200 kb
Host smart-ecb87b88-75f5-469e-b899-7bdb2409abf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234146189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.4234146189
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.190193968
Short name T932
Test name
Test status
Simulation time 45315575 ps
CPU time 0.72 seconds
Started May 19 01:54:47 PM PDT 24
Finished May 19 01:54:51 PM PDT 24
Peak memory 205584 kb
Host smart-757e37a7-09fb-4586-8a24-7f2c0de05a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190193968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.190193968
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2662923465
Short name T585
Test name
Test status
Simulation time 260003910 ps
CPU time 1.84 seconds
Started May 19 01:54:55 PM PDT 24
Finished May 19 01:55:05 PM PDT 24
Peak memory 216024 kb
Host smart-874e8a05-0bdb-4bea-a28d-788a5f1b4a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662923465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2662923465
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4259763964
Short name T564
Test name
Test status
Simulation time 546883036 ps
CPU time 6.97 seconds
Started May 19 01:54:44 PM PDT 24
Finished May 19 01:54:53 PM PDT 24
Peak memory 217492 kb
Host smart-2fdbf0f7-cd49-42ee-8f66-af783702e444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259763964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4259763964
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4168705146
Short name T373
Test name
Test status
Simulation time 85809560 ps
CPU time 0.77 seconds
Started May 19 01:54:46 PM PDT 24
Finished May 19 01:54:50 PM PDT 24
Peak memory 205836 kb
Host smart-299fec11-ea55-4403-9739-64927a00befa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168705146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4168705146
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2918362620
Short name T441
Test name
Test status
Simulation time 145112223 ps
CPU time 2.16 seconds
Started May 19 01:54:41 PM PDT 24
Finished May 19 01:54:44 PM PDT 24
Peak memory 212648 kb
Host smart-8350eb47-cadc-4855-aad9-f2f00bb8e508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918362620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2918362620
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1581485330
Short name T758
Test name
Test status
Simulation time 56923539 ps
CPU time 0.74 seconds
Started May 19 01:55:09 PM PDT 24
Finished May 19 01:55:12 PM PDT 24
Peak memory 204728 kb
Host smart-1067712d-dc46-45e0-8955-2249f3342fde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581485330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
581485330
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.4085893688
Short name T598
Test name
Test status
Simulation time 150549889 ps
CPU time 2.14 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:55:03 PM PDT 24
Peak memory 218780 kb
Host smart-1fec6435-8151-46e1-ad92-26eaa42299de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085893688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.4085893688
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2246791849
Short name T735
Test name
Test status
Simulation time 50280003 ps
CPU time 0.72 seconds
Started May 19 01:54:42 PM PDT 24
Finished May 19 01:54:44 PM PDT 24
Peak memory 205408 kb
Host smart-3cf44393-ed93-4923-bf7e-46000e69ba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246791849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2246791849
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2263474240
Short name T717
Test name
Test status
Simulation time 15064185450 ps
CPU time 48.62 seconds
Started May 19 01:55:00 PM PDT 24
Finished May 19 01:55:54 PM PDT 24
Peak memory 234276 kb
Host smart-aca97b4e-4aaf-4903-ab8a-7f521db490ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263474240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2263474240
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1178971544
Short name T888
Test name
Test status
Simulation time 33574301290 ps
CPU time 198.15 seconds
Started May 19 01:54:47 PM PDT 24
Finished May 19 01:58:09 PM PDT 24
Peak memory 273064 kb
Host smart-391b5d96-21ec-449f-9d36-8f85905dac36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178971544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1178971544
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.4120669282
Short name T31
Test name
Test status
Simulation time 741602083953 ps
CPU time 493.16 seconds
Started May 19 01:54:50 PM PDT 24
Finished May 19 02:03:11 PM PDT 24
Peak memory 260984 kb
Host smart-b78f2b2f-a212-4674-aebb-5c30d56a1d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120669282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.4120669282
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.4009534470
Short name T834
Test name
Test status
Simulation time 4126299454 ps
CPU time 18.42 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:20 PM PDT 24
Peak memory 241084 kb
Host smart-7efa69eb-e513-4d36-85a7-5a80dcf975ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009534470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.4009534470
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.978245359
Short name T967
Test name
Test status
Simulation time 1093333704 ps
CPU time 6.08 seconds
Started May 19 01:54:47 PM PDT 24
Finished May 19 01:54:58 PM PDT 24
Peak memory 233348 kb
Host smart-4f4f8294-b894-4258-a626-a44545e76a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978245359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.978245359
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1442516247
Short name T169
Test name
Test status
Simulation time 36891427 ps
CPU time 2.4 seconds
Started May 19 01:54:47 PM PDT 24
Finished May 19 01:54:54 PM PDT 24
Peak memory 221524 kb
Host smart-8fee5d97-ad3a-4d9b-8ecf-03b745f1d7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442516247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1442516247
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.457950449
Short name T533
Test name
Test status
Simulation time 61049633 ps
CPU time 1.09 seconds
Started May 19 01:54:36 PM PDT 24
Finished May 19 01:54:38 PM PDT 24
Peak memory 216776 kb
Host smart-3c330b63-f181-49a2-a408-e95d8a0e4096
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457950449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.457950449
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3855399516
Short name T340
Test name
Test status
Simulation time 82380459166 ps
CPU time 11.56 seconds
Started May 19 01:54:48 PM PDT 24
Finished May 19 01:55:04 PM PDT 24
Peak memory 218544 kb
Host smart-b1373db0-c183-43f7-849b-f36d67597e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855399516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3855399516
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3137818689
Short name T183
Test name
Test status
Simulation time 947267106 ps
CPU time 8.62 seconds
Started May 19 01:54:51 PM PDT 24
Finished May 19 01:55:07 PM PDT 24
Peak memory 232752 kb
Host smart-4591afbf-19b6-49ba-b36b-1412231783f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137818689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3137818689
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.775391652
Short name T530
Test name
Test status
Simulation time 250809885 ps
CPU time 5.58 seconds
Started May 19 01:54:47 PM PDT 24
Finished May 19 01:54:57 PM PDT 24
Peak memory 222564 kb
Host smart-7580f74a-a8ca-42d0-b679-8a218de7a0e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=775391652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.775391652
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1679551970
Short name T154
Test name
Test status
Simulation time 13245623578 ps
CPU time 93.11 seconds
Started May 19 01:54:50 PM PDT 24
Finished May 19 01:56:29 PM PDT 24
Peak memory 237268 kb
Host smart-505ccbfb-668d-4b44-8f0d-96187481e917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679551970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1679551970
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2004434426
Short name T736
Test name
Test status
Simulation time 2773410010 ps
CPU time 14.01 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:13 PM PDT 24
Peak memory 216708 kb
Host smart-f327f79c-f0de-4cda-a3e4-09ee0668f029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004434426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2004434426
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1298352309
Short name T569
Test name
Test status
Simulation time 16793789580 ps
CPU time 14.06 seconds
Started May 19 01:54:48 PM PDT 24
Finished May 19 01:55:06 PM PDT 24
Peak memory 216468 kb
Host smart-ae7d80dd-f328-4c27-a45f-6cdc383924f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298352309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1298352309
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1049381360
Short name T787
Test name
Test status
Simulation time 155046071 ps
CPU time 1.48 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:54:57 PM PDT 24
Peak memory 216360 kb
Host smart-6859575d-5657-49ff-896f-32ffda14c5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049381360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1049381360
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1272061559
Short name T621
Test name
Test status
Simulation time 1161521177 ps
CPU time 0.85 seconds
Started May 19 01:54:45 PM PDT 24
Finished May 19 01:54:48 PM PDT 24
Peak memory 205780 kb
Host smart-61117886-7423-4ac4-b1f6-31a771d63ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272061559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1272061559
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.369067423
Short name T625
Test name
Test status
Simulation time 5017655895 ps
CPU time 14.9 seconds
Started May 19 01:54:50 PM PDT 24
Finished May 19 01:55:12 PM PDT 24
Peak memory 218896 kb
Host smart-73a3f702-aa47-4220-8afa-3db86ec4e509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369067423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.369067423
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3768916321
Short name T234
Test name
Test status
Simulation time 657002978 ps
CPU time 7.65 seconds
Started May 19 01:55:00 PM PDT 24
Finished May 19 01:55:14 PM PDT 24
Peak memory 219596 kb
Host smart-004d6d2c-bc57-4d75-b4b5-a3b660344e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768916321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3768916321
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.280786187
Short name T579
Test name
Test status
Simulation time 41445442 ps
CPU time 0.81 seconds
Started May 19 01:54:58 PM PDT 24
Finished May 19 01:55:06 PM PDT 24
Peak memory 206796 kb
Host smart-ffaf8f23-a685-4261-a4ee-6c56daf6952e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280786187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.280786187
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1739048681
Short name T226
Test name
Test status
Simulation time 9065676042 ps
CPU time 26.09 seconds
Started May 19 01:54:45 PM PDT 24
Finished May 19 01:55:13 PM PDT 24
Peak memory 235424 kb
Host smart-a3af3823-874a-4d8b-8f04-e5b14b93a9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739048681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1739048681
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2077843959
Short name T283
Test name
Test status
Simulation time 21336717528 ps
CPU time 107.88 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:56:46 PM PDT 24
Peak memory 253552 kb
Host smart-0038185d-5bdc-4e11-8a7c-97dd80329644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077843959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2077843959
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2317440687
Short name T81
Test name
Test status
Simulation time 16782922503 ps
CPU time 37.56 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:55:32 PM PDT 24
Peak memory 230312 kb
Host smart-23f6f44d-386c-4010-b467-eb7d8c81fbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317440687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2317440687
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1979512204
Short name T769
Test name
Test status
Simulation time 1532781242 ps
CPU time 22.6 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:55:16 PM PDT 24
Peak memory 240800 kb
Host smart-08067d46-9502-4497-a005-d64fc88a7d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979512204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1979512204
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3541714545
Short name T387
Test name
Test status
Simulation time 57663461 ps
CPU time 2.26 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:02 PM PDT 24
Peak memory 220836 kb
Host smart-1d8fd791-a3d0-4616-8be6-3e46c676a2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541714545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3541714545
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1237574139
Short name T639
Test name
Test status
Simulation time 18715554467 ps
CPU time 103.86 seconds
Started May 19 01:54:56 PM PDT 24
Finished May 19 01:56:48 PM PDT 24
Peak memory 230344 kb
Host smart-9e904bff-0da0-4ecc-b799-1470d04534ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237574139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1237574139
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.527293997
Short name T377
Test name
Test status
Simulation time 25164052 ps
CPU time 1.07 seconds
Started May 19 01:54:51 PM PDT 24
Finished May 19 01:54:59 PM PDT 24
Peak memory 216764 kb
Host smart-def7714d-d683-4ec9-876e-02edfe83310c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527293997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.527293997
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.962053086
Short name T782
Test name
Test status
Simulation time 6889661199 ps
CPU time 20.47 seconds
Started May 19 01:54:51 PM PDT 24
Finished May 19 01:55:19 PM PDT 24
Peak memory 238692 kb
Host smart-4b849e5c-78ca-483a-abe2-e8df646be6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962053086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
962053086
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2182409955
Short name T219
Test name
Test status
Simulation time 933500390 ps
CPU time 4 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:54:58 PM PDT 24
Peak memory 216712 kb
Host smart-f0a79d85-1f91-4b29-810b-d69c425bd71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182409955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2182409955
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1629311033
Short name T679
Test name
Test status
Simulation time 194470247 ps
CPU time 4.07 seconds
Started May 19 01:54:53 PM PDT 24
Finished May 19 01:55:05 PM PDT 24
Peak memory 219148 kb
Host smart-7a189d71-0d1b-44d3-9d16-23850724fc35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1629311033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1629311033
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1494705257
Short name T747
Test name
Test status
Simulation time 254425808 ps
CPU time 1.11 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:54:57 PM PDT 24
Peak memory 206924 kb
Host smart-13e031d6-2b62-4318-8db4-0e7505de74d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494705257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1494705257
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2955404616
Short name T876
Test name
Test status
Simulation time 8021179185 ps
CPU time 44.62 seconds
Started May 19 01:54:49 PM PDT 24
Finished May 19 01:55:40 PM PDT 24
Peak memory 216460 kb
Host smart-eba36583-5167-4844-8a9d-5c907e8bd63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955404616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2955404616
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.72774586
Short name T364
Test name
Test status
Simulation time 566885547 ps
CPU time 3.97 seconds
Started May 19 01:54:52 PM PDT 24
Finished May 19 01:55:03 PM PDT 24
Peak memory 216352 kb
Host smart-47f1c3d9-fe69-4e7b-9616-bb6837d26b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72774586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.72774586
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.840303963
Short name T566
Test name
Test status
Simulation time 37983631 ps
CPU time 0.69 seconds
Started May 19 01:54:46 PM PDT 24
Finished May 19 01:54:50 PM PDT 24
Peak memory 205520 kb
Host smart-c1b7075c-9704-4c3f-99ad-82c34a1ea566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840303963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.840303963
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.977104294
Short name T760
Test name
Test status
Simulation time 46590363 ps
CPU time 0.68 seconds
Started May 19 01:54:54 PM PDT 24
Finished May 19 01:55:03 PM PDT 24
Peak memory 205500 kb
Host smart-65d7026d-c43e-4852-93cd-350b8deb9b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977104294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.977104294
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2550932377
Short name T319
Test name
Test status
Simulation time 1343344090 ps
CPU time 6.09 seconds
Started May 19 01:54:50 PM PDT 24
Finished May 19 01:55:04 PM PDT 24
Peak memory 218460 kb
Host smart-71467668-0c4c-48f7-a012-f18cda91980c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550932377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2550932377
Directory /workspace/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%