Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2592284	1			T2	25		T3	1		T5	3
all_values[1]	2592284	1			T2	25		T3	1		T5	3
all_values[2]	2592284	1			T2	25		T3	1		T5	3
all_values[3]	2592284	1			T2	25		T3	1		T5	3
all_values[4]	2592284	1			T2	25		T3	1		T5	3
all_values[5]	2592284	1			T2	25		T3	1		T5	3
all_values[6]	2592284	1			T2	25		T3	1		T5	3
all_values[7]	2592284	1			T2	25		T3	1		T5	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20036233

1

T2

114

T3

8

T5

24

auto[1]

702039

1

T2

86

T14

5065

T62

104

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20717719

1

T2

106

T3

8

T5

24

auto[1]

20553

1

T2

94

T8

2

T13

67

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2453961	1			T2	10		T3	1		T5	3
all_values[0]	auto[0]	auto[1]	10523	1			T2	6		T13	65		T14	37
all_values[0]	auto[1]	auto[0]	127281	1			T2	5		T14	2		T62	9
all_values[0]	auto[1]	auto[1]	519	1			T2	4		T62	2		T63	1
all_values[1]	auto[0]	auto[0]	2505888	1			T2	8		T3	1		T5	3
all_values[1]	auto[0]	auto[1]	4823	1			T2	4		T13	2		T18	75
all_values[1]	auto[1]	auto[0]	81202	1			T2	5		T14	990		T62	8
all_values[1]	auto[1]	auto[1]	371	1			T2	8		T14	23		T62	3
all_values[2]	auto[0]	auto[0]	2476021	1			T2	10		T3	1		T5	3
all_values[2]	auto[0]	auto[1]	1846	1			T2	4		T21	71		T25	13
all_values[2]	auto[1]	auto[0]	114145	1			T2	4		T14	993		T62	6
all_values[2]	auto[1]	auto[1]	272	1			T2	7		T14	20		T62	3
all_values[3]	auto[0]	auto[0]	2557159	1			T2	9		T3	1		T5	3
all_values[3]	auto[0]	auto[1]	202	1			T2	4		T62	1		T63	1
all_values[3]	auto[1]	auto[0]	34698	1			T2	4		T14	1009		T62	8
all_values[3]	auto[1]	auto[1]	225	1			T2	8		T14	3		T62	10
all_values[4]	auto[0]	auto[0]	2495897	1			T2	7		T3	1		T5	3
all_values[4]	auto[0]	auto[1]	206	1			T2	11		T14	1		T62	4
all_values[4]	auto[1]	auto[0]	95957	1			T2	3		T62	10		T63	1
all_values[4]	auto[1]	auto[1]	224	1			T2	4		T62	6		T63	2
all_values[5]	auto[0]	auto[0]	2463738	1			T2	8		T3	1		T5	3
all_values[5]	auto[0]	auto[1]	325	1			T2	3		T8	2		T14	1
all_values[5]	auto[1]	auto[0]	128016	1			T2	9		T14	1011		T62	6
all_values[5]	auto[1]	auto[1]	205	1			T2	5		T62	5		T63	1
all_values[6]	auto[0]	auto[0]	2561044	1			T2	5		T3	1		T5	3
all_values[6]	auto[0]	auto[1]	195	1			T2	13		T62	3		T63	3
all_values[6]	auto[1]	auto[0]	30839	1			T2	1		T14	1012		T62	10
all_values[6]	auto[1]	auto[1]	206	1			T2	6		T62	6		T63	3
all_values[7]	auto[0]	auto[0]	2504188	1			T2	10		T3	1		T5	3
all_values[7]	auto[0]	auto[1]	217	1			T2	2		T62	2		T63	5
all_values[7]	auto[1]	auto[0]	87685	1			T2	8		T14	1		T62	3
all_values[7]	auto[1]	auto[1]	194	1			T2	5		T14	1		T62	9