Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	24481	1			T6	12		T7	6		T13	342
auto[SpiFlashAddrCfg]	5870	1			T3	4		T11	4		T13	103
auto[SpiFlashAddr3b]	6868	1			T3	12		T5	1		T11	2
auto[SpiFlashAddr4b]	5876	1			T3	6		T5	1		T12	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24656

1

T3

22

T5

2

T6

12

auto[1]

18439

1

T11

8

T13

314

T14

467

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23513

1

T3

16

T5

1

T6

12

auto[1]

19582

1

T3

6

T5

1

T12

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	27989	1			T3	8		T6	12		T7	6
values[1]	807	1			T13	14		T14	8		T36	2
values[2]	1122	1			T13	18		T14	12		T18	4
values[3]	1109	1			T3	4		T12	2		T13	25
values[4]	1213	1			T13	19		T14	11		T18	12
values[5]	1064	1			T13	19		T14	8		T18	16
values[6]	1160	1			T13	27		T14	12		T26	4
values[7]	1159	1			T3	6		T13	17		T14	16
values[8]	7472	1			T3	4		T5	2		T11	8

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20862

1

T3

22

T6

12

T7

6

auto[1]

22233

1

T5

2

T18

434

T21

216

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

41529

1

T3

22

T5

2

T6

12

write

1566

1

T13

33

T14

23

T26

4

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

15220

1

T3

10

T5

1

T6

12

valids[0x1]

27875

1

T3

12

T5

1

T11

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1186	1			T13	20		T14	10		T18	9
internal_process_ops[0x5a]	1178	1			T3	8		T13	14		T14	9
internal_process_ops[0x05]	13933	1			T13	204		T14	436		T18	164
internal_process_ops[0x35]	1135	1			T13	16		T14	8		T18	11
internal_process_ops[0x15]	1225	1			T13	15		T14	9		T18	13
internal_process_ops[0x03]	832	1			T3	4		T5	1		T13	16
internal_process_ops[0x0b]	869	1			T11	2		T13	21		T14	11
internal_process_ops[0x3b]	787	1			T13	18		T14	12		T20	5
internal_process_ops[0x6b]	829	1			T13	22		T14	12		T18	6
internal_process_ops[0xbb]	891	1			T3	6		T5	1		T12	2
internal_process_ops[0xeb]	774	1			T3	4		T13	14		T14	7

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42340

1

T3

22

T5

2

T6

12

auto[1]

755

1

T13

22

T14

16

T18

13

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41589

1

T3

22

T5

2

T6

12

auto[1]

1506

1

T13

19

T14

25

T18

21

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

6969

1

T6

12

T7

6

T13

195

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

3628

1

T13

140

T14

377

T20

53

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1714

1

T3

4

T13

57

T14

22

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1350

1

T11

4

T13

36

T14

24

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1923

1

T3

12

T13

50

T14

34

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1575

1

T11

2

T13

68

T14

25

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1609

1

T3

6

T12

2

T13

41

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1389

1

T11

2

T13

47

T14

28

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

53

1

T14

1

T26

4

T31

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

30

1

T13

2

T14

3

T28

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

32

1

T13

1

T30

2

T52

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

48

1

T13

4

T31

2

T34

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

56

1

T13

2

T31

2

T264

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

31

1

T14

1

T20

1

T32

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

33

1

T13

3

T14

2

T47

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

43

1

T13

5

T30

2

T33

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

48

1

T31

2

T34

1

T51

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

47

1

T13

4

T14

5

T31

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

41

1

T14

2

T30

1

T32

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

46

1

T13

3

T29

2

T32

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

39

1

T20

5

T30

1

T34

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

35

1

T13

2

T20

1

T30

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

69

1

T13

5

T14

2

T30

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

54

1

T13

2

T14

7

T27

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7739

1

T18

136

T21

67

T25

67

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5777

1

T18

118

T21

44

T25

17

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1198

1

T18

27

T21

8

T25

11

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1262

1

T18

22

T21

8

T25

19

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1497

1

T5

1

T18

24

T21

20

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1483

1

T18

29

T21

15

T25

21

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1234

1

T5

1

T18

19

T21

15

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1182

1

T18

42

T21

27

T25

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

54

1

T18

1

T21

1

T44

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

36

1

T265

1

T62

3

T266

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

62

1

T44

1

T62

1

T267

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

53

1

T21

2

T25

3

T44

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

43

1

T25

1

T46

1

T268

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

45

1

T265

2

T268

3

T269

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

37

1

T18

2

T45

1

T266

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

58

1

T18

3

T45

1

T46

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

48

1

T21

3

T62

3

T70

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

62

1

T18

4

T45

4

T46

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

53

1

T18

1

T25

1

T46

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

45

1

T18

4

T25

1

T46

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

75

1

T21

2

T86

1

T62

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

71

1

T18

2

T21

1

T25

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

68

1

T21

1

T44

2

T45

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

51

1

T21

2

T45

1

T62

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3021	1			T6	12		T7	6		T13	78
auto[0]	values[0]	valids[0x1]	9545	1			T3	8		T13	326		T14	504
auto[0]	values[1]	valids[0x1]	391	1			T13	14		T14	8		T36	2
auto[0]	values[2]	valids[0x0]	428	1			T13	11		T14	9		T20	14
auto[0]	values[2]	valids[0x1]	207	1			T13	7		T14	3		T20	8
auto[0]	values[3]	valids[0x0]	405	1			T3	4		T12	2		T13	13
auto[0]	values[3]	valids[0x1]	198	1			T13	12		T14	4		T20	6
auto[0]	values[4]	valids[0x0]	443	1			T13	11		T14	3		T20	9
auto[0]	values[4]	valids[0x1]	224	1			T13	8		T14	8		T20	6
auto[0]	values[5]	valids[0x0]	379	1			T13	14		T14	7		T20	2
auto[0]	values[5]	valids[0x1]	192	1			T13	5		T14	1		T20	4
auto[0]	values[6]	valids[0x0]	409	1			T13	19		T14	4		T26	4
auto[0]	values[6]	valids[0x1]	236	1			T13	8		T14	8		T20	4
auto[0]	values[7]	valids[0x0]	447	1			T3	6		T13	9		T14	12
auto[0]	values[7]	valids[0x1]	200	1			T13	8		T14	4		T20	1
auto[0]	values[8]	valids[0x0]	2625	1			T11	4		T13	84		T14	37
auto[0]	values[8]	valids[0x1]	1512	1			T3	4		T11	4		T13	40
auto[1]	values[0]	valids[0x0]	3337	1			T18	67		T21	37		T25	23
auto[1]	values[0]	valids[0x1]	12086	1			T18	227		T21	101		T25	65
auto[1]	values[1]	valids[0x1]	416	1			T18	16		T21	1		T44	1
auto[1]	values[2]	valids[0x0]	303	1			T18	2		T21	2		T25	2
auto[1]	values[2]	valids[0x1]	184	1			T18	2		T21	1		T25	2
auto[1]	values[3]	valids[0x0]	319	1			T18	10		T21	3		T25	4
auto[1]	values[3]	valids[0x1]	187	1			T18	2		T21	5		T44	3
auto[1]	values[4]	valids[0x0]	298	1			T18	9		T21	4		T25	6
auto[1]	values[4]	valids[0x1]	248	1			T18	3		T21	10		T25	1
auto[1]	values[5]	valids[0x0]	292	1			T18	8		T21	4		T25	5
auto[1]	values[5]	valids[0x1]	201	1			T18	8		T21	5		T25	4
auto[1]	values[6]	valids[0x0]	280	1			T18	9		T21	6		T25	4
auto[1]	values[6]	valids[0x1]	235	1			T18	4		T21	5		T25	6
auto[1]	values[7]	valids[0x0]	310	1			T18	5		T21	3		T25	5
auto[1]	values[7]	valids[0x1]	202	1			T18	4		T21	4		T25	4
auto[1]	values[8]	valids[0x0]	1924	1			T5	1		T18	37		T21	22
auto[1]	values[8]	valids[0x1]	1411	1			T5	1		T18	21		T21	3