Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2783106

1

T3

632

T5

249

T6

1610

auto[1]

12785

1

T13

187

T14

425

T18

154

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

993227

1

T3

632

T5

249

T6

1610

auto[1]

1802664

1

T13

30346

T14

22756

T18

17657

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	557315	1			T3	40		T5	58		T6	599
auto[524288:1048575]	331747	1			T3	211		T6	24		T13	1953
auto[1048576:1572863]	265447	1			T3	113		T13	5067		T14	135
auto[1572864:2097151]	349859	1			T3	16		T7	703		T12	2
auto[2097152:2621439]	351140	1			T3	153		T5	190		T7	455
auto[2621440:3145727]	304005	1			T3	37		T5	1		T6	116
auto[3145728:3670015]	317117	1			T3	37		T6	289		T7	985
auto[3670016:4194303]	319261	1			T3	25		T6	582		T7	596

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1822849

1

T3

241

T5

104

T6

104

auto[1]

973042

1

T3

391

T5

145

T6

1506

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2502016

1

T3

632

T5

249

T6

1602

auto[1]

293875

1

T6

8

T13

6160

T14

449

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	204971	1			T3	40		T5	58		T6	599
auto[0]	auto[0]	auto[0:524287]	auto[1]	309832	1			T13	4644		T14	4010		T18	910
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	123364	1			T3	211		T6	24		T13	10
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	181905	1			T13	1943		T14	3628		T18	1363
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	67983	1			T3	113		T13	9		T14	10
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	160896	1			T13	3277		T14	11		T18	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	124412	1			T3	16		T7	703		T12	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	186068	1			T13	3024		T14	2270		T18	7807
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	130730	1			T3	153		T5	190		T7	455
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	174591	1			T13	3521		T14	4		T18	3124
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	107039	1			T3	37		T5	1		T6	108
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	161872	1			T13	1029		T14	899		T18	1251
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	116743	1			T3	37		T6	289		T7	985
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	163532	1			T13	6333		T14	7521		T18	260
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	109315	1			T3	25		T6	582		T7	596
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	168513	1			T13	260		T14	3575		T18	2
auto[0]	auto[1]	auto[0:524287]	auto[0]	1103	1			T13	5		T14	2		T35	207
auto[0]	auto[1]	auto[0:524287]	auto[1]	39188	1			T13	1407		T14	438		T18	257
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	799	1			T37	47		T18	4		T20	9
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	24345	1			T20	1114		T21	128		T45	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1733	1			T13	2		T14	1		T18	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	33089	1			T13	1779		T18	2200		T20	2702
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	814	1			T13	3		T14	1		T18	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	36503	1			T18	137		T265	1465		T266	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	191	1			T37	16		T18	1		T20	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	43968	1			T18	210		T21	2940		T46	513
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1572	1			T6	8		T14	1		T37	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	31955	1			T18	1		T20	128		T46	129
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	301	1			T14	1		T20	6		T21	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	35484	1			T21	128		T265	258		T30	769
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	650	1			T13	3		T14	1		T35	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	39645	1			T13	2961		T20	1		T25	256
auto[1]	auto[0]	auto[0:524287]	auto[0]	231	1			T13	6		T14	2		T18	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	1665	1			T13	31		T14	2		T18	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	146	1			T14	10		T18	3		T20	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	969	1			T14	178		T18	16		T20	86
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	135	1			T14	3		T18	1		T21	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1042	1			T14	110		T18	3		T21	10
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	180	1			T13	2		T14	4		T18	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1391	1			T13	13		T14	24		T18	44
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	150	1			T13	5		T14	4		T18	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1285	1			T13	100		T14	80		T18	21
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	149	1			T13	1		T14	1		T18	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1095	1			T13	2		T14	3		T21	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	123	1			T13	1		T18	1		T20	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	792	1			T13	10		T18	25		T20	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	127	1			T13	4		T18	2		T20	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	770	1			T13	12		T18	2		T20	12
auto[1]	auto[1]	auto[0:524287]	auto[0]	33	1			T14	1		T18	1		T265	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	292	1			T14	3		T18	14		T265	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	26	1			T20	1		T45	1		T86	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	193	1			T20	7		T45	2		T86	8
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	42	1			T86	1		T30	1		T266	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	527	1			T86	1		T266	4		T287	9
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	33	1			T18	1		T265	1		T34	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	458	1			T18	2		T265	25		T34	23
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	28	1			T46	1		T32	1		T267	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	197	1			T46	12		T267	7		T287	7
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	41	1			T18	1		T46	1		T32	7
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	282	1			T18	4		T32	3		T180	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	26	1			T265	1		T278	1		T129	5
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	116	1			T265	35		T278	5		T301	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	37	1			T20	1		T45	1		T31	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	204	1			T45	1		T287	1		T52	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1523966	1			T3	241		T5	104		T6	102
auto[0]	auto[0]	auto[1]	967800	1			T3	391		T5	145		T6	1500
auto[0]	auto[1]	auto[0]	286337	1			T6	2		T13	6160		T14	445
auto[0]	auto[1]	auto[1]	5003	1			T6	6		T35	204		T37	8
auto[1]	auto[0]	auto[0]	10052	1			T13	186		T14	421		T18	124
auto[1]	auto[0]	auto[1]	198	1			T13	1		T18	7		T25	1
auto[1]	auto[1]	auto[0]	2494	1			T14	3		T18	23		T20	8
auto[1]	auto[1]	auto[1]	41	1			T14	1		T20	1		T266	1