Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12554

1

T3

22

T6

12

T7

6

auto[1]

8308

1

T11

8

T13

314

T14

467

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2732	1			T14	240		T94	16		T198	10
values[1]	2348	1			T6	12		T12	2		T13	63
values[2]	2565	1			T13	185		T14	81		T20	83
values[3]	2635	1			T13	98		T14	25		T37	16
values[4]	3059	1			T13	109		T36	2		T20	20
values[5]	2916	1			T13	46		T14	173		T20	118
values[6]	2338	1			T3	22		T11	8		T13	71
values[7]	2269	1			T7	6		T13	95		T14	124

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2044	1			T11	8		T13	70		T14	131
values[1]	2966	1			T3	22		T13	74		T14	104
values[2]	2689	1			T12	2		T13	161		T14	98
values[3]	2827	1			T13	170		T14	20		T36	2
values[4]	2550	1			T13	108		T14	110		T20	20
values[5]	2513	1			T13	20		T14	201		T26	16
values[6]	2613	1			T6	12		T13	44		T37	16
values[7]	2660	1			T7	6		T13	20		T14	41

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	94	1			T14	10		T95	10		T132	2
auto[0]	values[0]	values[1]	259	1			T198	10		T34	15		T184	11
auto[0]	values[0]	values[2]	169	1			T209	16		T128	8		T81	11
auto[0]	values[0]	values[3]	345	1			T218	14		T184	10		T302	10
auto[0]	values[0]	values[4]	191	1			T31	22		T32	14		T51	31
auto[0]	values[0]	values[5]	152	1			T14	18		T303	6		T304	2
auto[0]	values[0]	values[6]	198	1			T189	25		T234	9		T305	16
auto[0]	values[0]	values[7]	251	1			T179	4		T47	18		T181	13
auto[0]	values[1]	values[0]	190	1			T204	14		T128	17		T189	14
auto[0]	values[1]	values[1]	221	1			T35	12		T75	4		T180	12
auto[0]	values[1]	values[2]	180	1			T12	2		T13	6		T14	10
auto[0]	values[1]	values[3]	81	1			T13	14		T173	12		T32	7
auto[0]	values[1]	values[4]	235	1			T205	8		T51	21		T180	13
auto[0]	values[1]	values[5]	230	1			T13	14		T34	7		T38	10
auto[0]	values[1]	values[6]	147	1			T6	12		T51	5		T181	10
auto[0]	values[1]	values[7]	176	1			T170	8		T32	7		T306	14
auto[0]	values[2]	values[0]	75	1			T31	12		T51	14		T128	11
auto[0]	values[2]	values[1]	235	1			T51	25		T213	2		T296	14
auto[0]	values[2]	values[2]	231	1			T13	59		T14	15		T47	17
auto[0]	values[2]	values[3]	351	1			T13	58		T14	9		T20	80
auto[0]	values[2]	values[4]	163	1			T32	30		T128	8		T184	11
auto[0]	values[2]	values[5]	53	1			T31	17		T307	14		T91	4
auto[0]	values[2]	values[6]	206	1			T13	12		T185	6		T52	8
auto[0]	values[2]	values[7]	172	1			T14	11		T34	21		T47	8
auto[0]	values[3]	values[0]	119	1			T13	32		T30	8		T31	13
auto[0]	values[3]	values[1]	179	1			T13	10		T20	18		T150	12
auto[0]	values[3]	values[2]	328	1			T34	8		T51	8		T218	14
auto[0]	values[3]	values[3]	179	1			T13	9		T31	15		T77	12
auto[0]	values[3]	values[4]	192	1			T14	16		T20	6		T59	4
auto[0]	values[3]	values[5]	177	1			T26	16		T20	13		T221	10
auto[0]	values[3]	values[6]	164	1			T37	16		T128	7		T282	4
auto[0]	values[3]	values[7]	173	1			T28	15		T47	11		T234	14
auto[0]	values[4]	values[0]	132	1			T32	10		T288	14		T184	14
auto[0]	values[4]	values[1]	180	1			T13	15		T76	10		T214	14
auto[0]	values[4]	values[2]	299	1			T13	5		T51	13		T224	22
auto[0]	values[4]	values[3]	410	1			T36	2		T31	17		T32	11
auto[0]	values[4]	values[4]	159	1			T13	9		T308	2		T181	13
auto[0]	values[4]	values[5]	280	1			T34	76		T129	12		T218	18
auto[0]	values[4]	values[6]	228	1			T30	11		T47	8		T129	14
auto[0]	values[4]	values[7]	209	1			T13	13		T20	9		T30	11
auto[0]	values[5]	values[0]	265	1			T13	10		T180	20		T181	25
auto[0]	values[5]	values[1]	78	1			T188	12		T32	8		T309	13
auto[0]	values[5]	values[2]	252	1			T32	14		T177	10		T200	12
auto[0]	values[5]	values[3]	148	1			T13	19		T128	11		T283	25
auto[0]	values[5]	values[4]	166	1			T14	10		T32	12		T52	8
auto[0]	values[5]	values[5]	376	1			T14	89		T20	14		T42	12
auto[0]	values[5]	values[6]	181	1			T28	16		T52	16		T180	14
auto[0]	values[5]	values[7]	247	1			T14	12		T20	54		T31	10
auto[0]	values[6]	values[0]	126	1			T31	18		T34	13		T128	19
auto[0]	values[6]	values[1]	410	1			T3	22		T20	13		T166	78
auto[0]	values[6]	values[2]	124	1			T47	13		T218	30		T194	13
auto[0]	values[6]	values[3]	130	1			T13	22		T52	12		T189	12
auto[0]	values[6]	values[4]	241	1			T13	11		T14	11		T51	13
auto[0]	values[6]	values[5]	122	1			T310	11		T311	17		T233	24
auto[0]	values[6]	values[6]	217	1			T13	15		T103	2		T174	10
auto[0]	values[6]	values[7]	136	1			T20	16		T260	8		T81	8
auto[0]	values[7]	values[0]	92	1			T180	17		T218	14		T312	10
auto[0]	values[7]	values[1]	148	1			T14	15		T31	15		T34	11
auto[0]	values[7]	values[2]	126	1			T13	10		T14	12		T192	5
auto[0]	values[7]	values[3]	188	1			T28	11		T52	13		T128	10
auto[0]	values[7]	values[4]	190	1			T13	10		T30	12		T219	10
auto[0]	values[7]	values[5]	174	1			T31	15		T34	7		T52	34
auto[0]	values[7]	values[6]	172	1			T20	14		T32	11		T51	15
auto[0]	values[7]	values[7]	232	1			T7	6		T20	16		T192	8
auto[1]	values[0]	values[0]	191	1			T14	121		T94	16		T180	12
auto[1]	values[0]	values[1]	154	1			T34	5		T184	9		T181	7
auto[1]	values[0]	values[2]	81	1			T128	12		T81	10		T194	11
auto[1]	values[0]	values[3]	116	1			T218	6		T184	10		T181	7
auto[1]	values[0]	values[4]	102	1			T31	18		T32	6		T51	14
auto[1]	values[0]	values[5]	154	1			T14	91		T311	7		T229	15
auto[1]	values[0]	values[6]	93	1			T189	4		T234	11		T233	9
auto[1]	values[0]	values[7]	182	1			T47	10		T181	14		T81	7
auto[1]	values[1]	values[0]	95	1			T128	3		T189	6		T234	10
auto[1]	values[1]	values[1]	151	1			T180	11		T184	9		T181	10
auto[1]	values[1]	values[2]	135	1			T13	17		T14	28		T30	10
auto[1]	values[1]	values[3]	41	1			T13	6		T32	13		T184	11
auto[1]	values[1]	values[4]	83	1			T51	22		T180	7		T194	18
auto[1]	values[1]	values[5]	164	1			T13	6		T34	13		T51	11
auto[1]	values[1]	values[6]	72	1			T51	15		T181	11		T175	6
auto[1]	values[1]	values[7]	147	1			T32	13		T189	44		T186	12
auto[1]	values[2]	values[0]	113	1			T31	8		T182	18		T208	8
auto[1]	values[2]	values[1]	146	1			T51	28		T296	6		T249	11
auto[1]	values[2]	values[2]	162	1			T13	29		T14	25		T220	14
auto[1]	values[2]	values[3]	141	1			T13	15		T14	11		T20	3
auto[1]	values[2]	values[4]	148	1			T32	12		T128	25		T184	9
auto[1]	values[2]	values[5]	33	1			T31	5		T313	14		T232	14
auto[1]	values[2]	values[6]	166	1			T13	12		T52	12		T234	5
auto[1]	values[2]	values[7]	170	1			T14	10		T34	19		T47	12
auto[1]	values[3]	values[0]	147	1			T13	18		T30	14		T31	9
auto[1]	values[3]	values[1]	237	1			T13	18		T20	22		T212	16
auto[1]	values[3]	values[2]	143	1			T34	12		T51	12		T218	37
auto[1]	values[3]	values[3]	126	1			T13	11		T31	9		T128	9
auto[1]	values[3]	values[4]	108	1			T14	9		T20	14		T128	8
auto[1]	values[3]	values[5]	99	1			T20	7		T194	43		T277	6
auto[1]	values[3]	values[6]	182	1			T128	13		T81	12		T228	8
auto[1]	values[3]	values[7]	82	1			T28	5		T47	9		T234	6
auto[1]	values[4]	values[0]	115	1			T32	15		T184	6		T234	6
auto[1]	values[4]	values[1]	198	1			T13	31		T189	11		T296	6
auto[1]	values[4]	values[2]	108	1			T13	18		T51	7		T81	22
auto[1]	values[4]	values[3]	265	1			T31	5		T32	10		T51	6
auto[1]	values[4]	values[4]	102	1			T13	11		T181	7		T81	19
auto[1]	values[4]	values[5]	137	1			T27	20		T34	12		T129	9
auto[1]	values[4]	values[6]	87	1			T30	9		T47	12		T129	13
auto[1]	values[4]	values[7]	150	1			T13	7		T20	11		T30	10
auto[1]	values[5]	values[0]	140	1			T13	10		T180	8		T181	15
auto[1]	values[5]	values[1]	103	1			T32	13		T309	22		T243	11
auto[1]	values[5]	values[2]	113	1			T32	10		T200	8		T181	4
auto[1]	values[5]	values[3]	97	1			T13	7		T128	11		T283	6
auto[1]	values[5]	values[4]	172	1			T14	51		T32	8		T52	12
auto[1]	values[5]	values[5]	160	1			T14	3		T20	9		T187	6
auto[1]	values[5]	values[6]	275	1			T28	5		T52	4		T180	6
auto[1]	values[5]	values[7]	143	1			T14	8		T20	41		T31	10
auto[1]	values[6]	values[0]	81	1			T11	8		T31	4		T34	7
auto[1]	values[6]	values[1]	77	1			T20	15		T47	13		T136	10
auto[1]	values[6]	values[2]	161	1			T47	9		T218	6		T194	7
auto[1]	values[6]	values[3]	59	1			T13	9		T52	10		T189	8
auto[1]	values[6]	values[4]	168	1			T13	9		T14	13		T29	28
auto[1]	values[6]	values[5]	88	1			T211	6		T310	9		T311	3
auto[1]	values[6]	values[6]	115	1			T13	5		T195	14		T206	9
auto[1]	values[6]	values[7]	83	1			T20	4		T260	27		T81	12
auto[1]	values[7]	values[0]	69	1			T180	8		T218	9		T202	5
auto[1]	values[7]	values[1]	190	1			T14	89		T31	7		T34	44
auto[1]	values[7]	values[2]	77	1			T13	17		T14	8		T192	15
auto[1]	values[7]	values[3]	150	1			T28	14		T52	7		T128	10
auto[1]	values[7]	values[4]	130	1			T13	58		T30	8		T260	3
auto[1]	values[7]	values[5]	114	1			T31	8		T34	29		T52	10
auto[1]	values[7]	values[6]	110	1			T20	6		T32	9		T51	10
auto[1]	values[7]	values[7]	107	1			T20	4		T192	12		T47	7