Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	301	1			T3	10		T13	9		T14	2
auto[ReadAddrCrossIntoMailbox]	267	1			T13	15		T14	4		T20	3
auto[ReadAddrCrossOutOfMailbox]	241	1			T13	8		T14	9		T20	1
auto[ReadAddrCrossAllMailbox]	169	1			T13	9		T14	3		T20	1
auto[ReadAddrOutsideMailbox]	2711	1			T3	4		T12	2		T11	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1803

1

T3

7

T12

1

T11

1

auto[1]

1886

1

T3

7

T12

1

T11

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	601	1			T3	4		T13	16		T14	14
read_ops[0x0b]	626	1			T11	2		T13	21		T14	11
read_ops[0x3b]	607	1			T13	18		T14	12		T20	5
read_ops[0x6b]	608	1			T13	22		T14	12		T20	7
read_ops[0xbb]	670	1			T3	6		T12	2		T13	19
read_ops[0xeb]	577	1			T3	4		T13	14		T14	7

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T3	2		T13	1		T30	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T3	2		T13	1		T31	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T20	1		T234	1		T186	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T13	3		T51	1		T181	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T14	1		T34	2		T291	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T13	1		T14	2		T31	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	8	1			T13	1		T128	1		T305	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T51	1		T181	3		T234	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	236	1			T13	7		T14	8		T20	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	198	1			T13	2		T14	3		T20	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T13	1		T20	1		T200	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T13	1		T30	1		T51	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T223	1		T52	2		T129	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T13	2		T30	1		T223	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T13	3		T20	1		T223	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T13	1		T14	3		T28	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T14	1		T296	1		T309	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T13	1		T30	1		T32	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	223	1			T11	1		T13	9		T14	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	222	1			T11	1		T13	3		T14	4
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T223	1		T31	2		T52	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	20	1			T223	1		T129	1		T194	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T13	1		T288	1		T186	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T14	1		T32	1		T128	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	14	1			T31	2		T77	1		T181	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T13	1		T14	1		T31	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T223	2		T34	1		T288	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T14	2		T223	2		T288	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	211	1			T13	8		T14	3		T20	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	251	1			T13	8		T14	5		T20	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T13	1		T14	1		T31	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T13	1		T14	1		T20	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T13	3		T14	1		T28	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T13	1		T30	1		T31	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T14	1		T31	2		T260	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	13	1			T32	1		T34	1		T189	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T13	1		T31	2		T51	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T13	2		T200	1		T181	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	217	1			T13	9		T14	6		T20	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	233	1			T13	4		T14	2		T20	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T3	2		T31	1		T181	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T3	2		T13	1		T32	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T13	3		T77	2		T298	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T13	1		T20	1		T77	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T28	1		T32	1		T234	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T13	1		T14	1		T52	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T13	1		T31	1		T128	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T13	2		T34	1		T52	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	237	1			T3	1		T12	1		T13	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	267	1			T3	1		T12	1		T13	7
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T3	1		T51	1		T218	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T3	1		T13	2		T30	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T13	1		T14	1		T31	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T14	1		T20	1		T30	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T13	1		T32	1		T129	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T32	2		T52	2		T128	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	8	1			T13	1		T180	1		T137	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T20	1		T31	2		T128	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	201	1			T3	1		T13	6		T14	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	215	1			T3	1		T13	3		T14	4