Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2592284	1			T2	25		T3	1		T5	3
all_pins[1]	2592284	1			T2	25		T3	1		T5	3
all_pins[2]	2592284	1			T2	25		T3	1		T5	3
all_pins[3]	2592284	1			T2	25		T3	1		T5	3
all_pins[4]	2592284	1			T2	25		T3	1		T5	3
all_pins[5]	2592284	1			T2	25		T3	1		T5	3
all_pins[6]	2592284	1			T2	25		T3	1		T5	3
all_pins[7]	2592284	1			T2	25		T3	1		T5	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20705142	1			T2	153		T3	8		T5	24
values[0x1]	33130	1			T2	47		T14	1113		T62	44
transitions[0x0=>0x1]	32102	1			T2	34		T14	1040		T62	31
transitions[0x1=>0x0]	32117	1			T2	35		T14	1040		T62	31

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2591729	1			T2	21		T3	1		T5	3
all_pins[0]	values[0x1]	555	1			T2	4		T62	2		T63	1
all_pins[0]	transitions[0x0=>0x1]	348	1			T2	3		T62	2		T30	3
all_pins[0]	transitions[0x1=>0x0]	188	1			T2	7		T14	35		T62	3
all_pins[1]	values[0x0]	2591889	1			T2	17		T3	1		T5	3
all_pins[1]	values[0x1]	395	1			T2	8		T14	35		T62	3
all_pins[1]	transitions[0x0=>0x1]	274	1			T2	4		T14	10		T62	3
all_pins[1]	transitions[0x1=>0x0]	161	1			T2	3		T62	3		T63	1
all_pins[2]	values[0x0]	2592002	1			T2	18		T3	1		T5	3
all_pins[2]	values[0x1]	282	1			T2	7		T14	25		T62	3
all_pins[2]	transitions[0x0=>0x1]	228	1			T2	5		T14	25		T62	2
all_pins[2]	transitions[0x1=>0x0]	171	1			T2	6		T14	3		T62	9
all_pins[3]	values[0x0]	2592059	1			T2	17		T3	1		T5	3
all_pins[3]	values[0x1]	225	1			T2	8		T14	3		T62	10
all_pins[3]	transitions[0x0=>0x1]	164	1			T2	7		T14	3		T62	7
all_pins[3]	transitions[0x1=>0x0]	163	1			T2	3		T62	3		T30	2
all_pins[4]	values[0x0]	2592060	1			T2	21		T3	1		T5	3
all_pins[4]	values[0x1]	224	1			T2	4		T62	6		T63	2
all_pins[4]	transitions[0x0=>0x1]	166	1			T2	3		T62	6		T63	2
all_pins[4]	transitions[0x1=>0x0]	1221	1			T2	4		T14	49		T62	5
all_pins[5]	values[0x0]	2591005	1			T2	20		T3	1		T5	3
all_pins[5]	values[0x1]	1279	1			T2	5		T14	49		T62	5
all_pins[5]	transitions[0x0=>0x1]	847	1			T2	5		T14	1		T62	2
all_pins[5]	transitions[0x1=>0x0]	29544	1			T2	6		T14	952		T62	3
all_pins[6]	values[0x0]	2562308	1			T2	19		T3	1		T5	3
all_pins[6]	values[0x1]	29976	1			T2	6		T14	1000		T62	6
all_pins[6]	transitions[0x0=>0x1]	29930	1			T2	3		T14	1000		T62	2
all_pins[6]	transitions[0x1=>0x0]	148	1			T2	2		T14	1		T62	5
all_pins[7]	values[0x0]	2592090	1			T2	20		T3	1		T5	3
all_pins[7]	values[0x1]	194	1			T2	5		T14	1		T62	9
all_pins[7]	transitions[0x0=>0x1]	145	1			T2	4		T14	1		T62	7
all_pins[7]	transitions[0x1=>0x0]	521	1			T2	4		T30	4		T172	2