Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	3	125	97.66

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	3	125	97.66	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2821	1			T11	8		T13	134		T14	38
values[1]	2809	1			T12	2		T13	70		T14	220
values[2]	2657	1			T13	134		T14	256		T37	16
values[3]	3091	1			T13	55		T14	40		T42	12
values[4]	2441	1			T13	121		T20	123		T28	25
values[5]	2183	1			T3	22		T13	50		T14	61
values[6]	2558	1			T13	20		T14	66		T20	71
values[7]	2302	1			T6	12		T7	6		T13	83

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2347	1			T14	144		T20	135		T173	12
values[1]	2142	1			T13	66		T20	60		T28	21
values[2]	2316	1			T14	92		T28	45		T174	10
values[3]	3024	1			T6	12		T13	78		T14	176
values[4]	2687	1			T3	22		T13	83		T14	61
values[5]	2888	1			T11	8		T13	234		T20	28
values[6]	2948	1			T7	6		T12	2		T13	186
values[7]	2510	1			T13	20		T14	144		T37	16

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20528

1

T3

22

T6

12

T7

6

auto[1]

334

1

T13

22

T14

16

T20

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	3	125	97.66	3

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	[values[7]]	0	1	1
[auto[1]]	[values[1]]	[values[5]]	0	1	1
[auto[1]]	[values[6]]	[values[3]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	321	1			T14	38		T20	70		T175	20
auto[0]	values[0]	values[1]	357	1			T20	20		T31	22		T38	10
auto[0]	values[0]	values[2]	188	1			T33	2		T176	6		T177	10
auto[0]	values[0]	values[3]	413	1			T13	54		T35	12		T178	14
auto[0]	values[0]	values[4]	266	1			T179	4		T51	21		T180	20
auto[0]	values[0]	values[5]	495	1			T11	8		T13	39		T31	20
auto[0]	values[0]	values[6]	499	1			T13	38		T51	25		T181	59
auto[0]	values[0]	values[7]	244	1			T77	12		T182	18		T133	24
auto[0]	values[1]	values[0]	239	1			T20	44		T103	2		T31	22
auto[0]	values[1]	values[1]	180	1			T13	25		T28	20		T183	2
auto[0]	values[1]	values[2]	486	1			T14	92		T34	20		T184	20
auto[0]	values[1]	values[3]	283	1			T32	20		T51	20		T129	20
auto[0]	values[1]	values[4]	292	1			T20	20		T185	6		T31	23
auto[0]	values[1]	values[5]	525	1			T52	42		T181	25		T186	20
auto[0]	values[1]	values[6]	436	1			T12	2		T13	43		T14	85
auto[0]	values[1]	values[7]	321	1			T14	40		T26	16		T187	6
auto[0]	values[2]	values[0]	290	1			T188	12		T31	22		T32	21
auto[0]	values[2]	values[1]	300	1			T32	20		T51	22		T189	20
auto[0]	values[2]	values[2]	290	1			T28	20		T76	10		T190	8
auto[0]	values[2]	values[3]	412	1			T14	145		T191	4		T132	2
auto[0]	values[2]	values[4]	262	1			T13	20		T95	10		T32	21
auto[0]	values[2]	values[5]	369	1			T13	113		T52	24		T180	20
auto[0]	values[2]	values[6]	293	1			T94	16		T192	20		T193	26
auto[0]	values[2]	values[7]	395	1			T14	102		T37	16		T31	22
auto[0]	values[3]	values[0]	421	1			T14	38		T42	12		T128	20
auto[0]	values[3]	values[1]	211	1			T71	4		T128	31		T194	20
auto[0]	values[3]	values[2]	383	1			T31	20		T189	48		T195	14
auto[0]	values[3]	values[3]	416	1			T13	23		T30	22		T196	88
auto[0]	values[3]	values[4]	530	1			T166	78		T197	10		T34	20
auto[0]	values[3]	values[5]	331	1			T30	21		T90	6		T128	23
auto[0]	values[3]	values[6]	227	1			T13	27		T198	10		T199	4
auto[0]	values[3]	values[7]	530	1			T34	106		T200	20		T180	23
auto[0]	values[4]	values[0]	162	1			T184	24		T201	4		T202	22
auto[0]	values[4]	values[1]	335	1			T13	19		T203	8		T189	20
auto[0]	values[4]	values[2]	278	1			T28	25		T174	10		T204	14
auto[0]	values[4]	values[3]	278	1			T34	40		T51	21		T52	20
auto[0]	values[4]	values[4]	378	1			T13	18		T20	83		T32	25
auto[0]	values[4]	values[5]	330	1			T13	53		T31	20		T194	39
auto[0]	values[4]	values[6]	425	1			T13	25		T20	40		T205	8
auto[0]	values[4]	values[7]	217	1			T129	26		T206	20		T207	8
auto[0]	values[5]	values[0]	278	1			T20	20		T173	12		T34	34
auto[0]	values[5]	values[1]	173	1			T20	20		T208	6		T51	16
auto[0]	values[5]	values[2]	187	1			T31	20		T209	16		T210	20
auto[0]	values[5]	values[3]	291	1			T29	26		T211	6		T31	20
auto[0]	values[5]	values[4]	331	1			T3	22		T13	21		T14	61
auto[0]	values[5]	values[5]	356	1			T13	25		T30	19		T32	24
auto[0]	values[5]	values[6]	287	1			T30	21		T212	16		T47	28
auto[0]	values[5]	values[7]	234	1			T34	53		T213	2		T181	27
auto[0]	values[6]	values[0]	349	1			T14	65		T27	18		T32	22
auto[0]	values[6]	values[1]	363	1			T20	20		T32	19		T214	14
auto[0]	values[6]	values[2]	228	1			T47	20		T51	32		T184	20
auto[0]	values[6]	values[3]	464	1			T75	4		T215	62		T216	14
auto[0]	values[6]	values[4]	284	1			T13	20		T217	2		T51	46
auto[0]	values[6]	values[5]	213	1			T20	27		T170	8		T218	73
auto[0]	values[6]	values[6]	328	1			T20	23		T219	10		T47	20
auto[0]	values[6]	values[7]	297	1			T32	19		T220	14		T47	20
auto[0]	values[7]	values[0]	241	1			T31	18		T180	25		T218	18
auto[0]	values[7]	values[1]	184	1			T13	20		T31	20		T32	20
auto[0]	values[7]	values[2]	245	1			T34	19		T221	10		T218	26
auto[0]	values[7]	values[3]	418	1			T6	12		T14	23		T150	12
auto[0]	values[7]	values[4]	307	1			T32	20		T81	23		T222	16
auto[0]	values[7]	values[5]	231	1			T223	22		T47	20		T128	20
auto[0]	values[7]	values[6]	395	1			T7	6		T13	43		T31	24
auto[0]	values[7]	values[7]	236	1			T13	19		T52	39		T224	22
auto[1]	values[0]	values[0]	3	1			T225	2		T226	1		-	-
auto[1]	values[0]	values[1]	2	1			T227	2		-	-		-	-
auto[1]	values[0]	values[2]	7	1			T33	2		T180	1		T137	1
auto[1]	values[0]	values[3]	8	1			T228	1		T229	3		T230	1
auto[1]	values[0]	values[4]	5	1			T136	1		T231	2		T232	2
auto[1]	values[0]	values[5]	7	1			T13	1		T31	2		T51	1
auto[1]	values[0]	values[6]	6	1			T13	2		T202	1		T233	1
auto[1]	values[1]	values[0]	6	1			T20	1		T128	2		T136	1
auto[1]	values[1]	values[1]	3	1			T13	1		T28	1		T225	1
auto[1]	values[1]	values[2]	2	1			T234	1		T202	1		-	-
auto[1]	values[1]	values[3]	4	1			T184	1		T193	1		T235	1
auto[1]	values[1]	values[4]	9	1			T52	2		T194	1		T236	2
auto[1]	values[1]	values[6]	13	1			T13	1		T14	3		T237	6
auto[1]	values[1]	values[7]	10	1			T189	1		T184	3		T50	4
auto[1]	values[2]	values[0]	8	1			T180	2		T186	1		T194	1
auto[1]	values[2]	values[1]	3	1			T51	1		T136	1		T238	1
auto[1]	values[2]	values[2]	5	1			T233	1		T229	2		T138	1
auto[1]	values[2]	values[3]	11	1			T14	7		T239	2		T230	1
auto[1]	values[2]	values[4]	4	1			T240	1		T241	1		T242	2
auto[1]	values[2]	values[5]	6	1			T13	1		T243	2		T244	3
auto[1]	values[2]	values[6]	3	1			T245	1		T50	1		T246	1
auto[1]	values[2]	values[7]	6	1			T14	2		T247	2		T248	2
auto[1]	values[3]	values[0]	6	1			T14	2		T239	1		T138	3
auto[1]	values[3]	values[1]	1	1			T137	1		-	-		-	-
auto[1]	values[3]	values[2]	4	1			T189	1		T181	1		T137	1
auto[1]	values[3]	values[3]	8	1			T13	1		T30	1		T210	1
auto[1]	values[3]	values[4]	4	1			T81	1		T249	2		T250	1
auto[1]	values[3]	values[5]	7	1			T128	3		T251	2		T138	1
auto[1]	values[3]	values[6]	7	1			T13	4		T138	1		T232	1
auto[1]	values[3]	values[7]	5	1			T34	2		T181	1		T238	1
auto[1]	values[4]	values[0]	2	1			T184	1		T252	1		-	-
auto[1]	values[4]	values[1]	7	1			T13	1		T210	3		T138	1
auto[1]	values[4]	values[2]	2	1			T250	2		-	-		-	-
auto[1]	values[4]	values[3]	6	1			T51	1		T243	1		T246	1
auto[1]	values[4]	values[4]	3	1			T13	2		T225	1		-	-
auto[1]	values[4]	values[5]	2	1			T194	1		T227	1		-	-
auto[1]	values[4]	values[6]	10	1			T13	3		T129	1		T231	6
auto[1]	values[4]	values[7]	6	1			T129	1		T206	1		T207	4
auto[1]	values[5]	values[0]	7	1			T34	2		T54	4		T253	1
auto[1]	values[5]	values[1]	9	1			T208	2		T51	4		T234	2
auto[1]	values[5]	values[2]	7	1			T31	2		T243	3		T254	2
auto[1]	values[5]	values[3]	8	1			T29	2		T181	2		T50	4
auto[1]	values[5]	values[4]	4	1			T13	2		T136	1		T246	1
auto[1]	values[5]	values[5]	6	1			T13	2		T30	1		T51	2
auto[1]	values[5]	values[6]	2	1			T30	1		T255	1		-	-
auto[1]	values[5]	values[7]	3	1			T34	2		T229	1		-	-
auto[1]	values[6]	values[0]	7	1			T14	1		T27	2		T128	1
auto[1]	values[6]	values[1]	6	1			T32	1		T218	1		T184	1
auto[1]	values[6]	values[2]	3	1			T256	1		T257	2		-	-
auto[1]	values[6]	values[4]	3	1			T81	1		T245	2		-	-
auto[1]	values[6]	values[5]	3	1			T20	1		T218	1		T258	1
auto[1]	values[6]	values[6]	8	1			T52	1		T181	1		T259	4
auto[1]	values[6]	values[7]	2	1			T32	1		T189	1		-	-
auto[1]	values[7]	values[0]	7	1			T31	2		T218	2		T239	1
auto[1]	values[7]	values[1]	8	1			T260	3		T261	2		T253	3
auto[1]	values[7]	values[2]	1	1			T34	1		-	-		-	-
auto[1]	values[7]	values[3]	4	1			T14	1		T30	1		T34	1
auto[1]	values[7]	values[4]	5	1			T238	3		T50	1		T243	1
auto[1]	values[7]	values[5]	7	1			T256	1		T262	6		-	-
auto[1]	values[7]	values[6]	9	1			T184	2		T181	1		T81	2
auto[1]	values[7]	values[7]	4	1			T13	1		T52	1		T263	2