Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1738

1

T10

2

T13

9

T17

8

auto[1]

1721

1

T10

1

T13

8

T17

16

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2048

1

T10

3

T13

16

T18

4

auto[1]

1411

1

T13

1

T17

24

T25

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2727

1

T10

3

T13

11

T17

24

auto[1]

732

1

T13

6

T18

2

T20

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	688	1			T10	1		T13	3		T17	5
valid[1]	695	1			T13	2		T17	4		T18	2
valid[2]	663	1			T10	1		T13	3		T17	2
valid[3]	707	1			T10	1		T13	6		T17	5
valid[4]	706	1			T13	3		T17	8		T18	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	147	1			T10	1		T13	1		T46	1
auto[0]	auto[0]	valid[0]	auto[1]	145	1			T17	1		T62	1		T87	3
auto[0]	auto[0]	valid[1]	auto[0]	124	1			T13	1		T25	2		T45	1
auto[0]	auto[0]	valid[1]	auto[1]	132	1			T17	1		T25	1		T62	1
auto[0]	auto[0]	valid[2]	auto[0]	132	1			T21	2		T28	1		T172	1
auto[0]	auto[0]	valid[2]	auto[1]	145	1			T17	2		T43	1		T86	1
auto[0]	auto[0]	valid[3]	auto[0]	140	1			T10	1		T13	4		T21	1
auto[0]	auto[0]	valid[3]	auto[1]	138	1			T43	1		T87	4		T89	2
auto[0]	auto[0]	valid[4]	auto[0]	124	1			T46	1		T28	1		T86	1
auto[0]	auto[0]	valid[4]	auto[1]	142	1			T17	4		T87	1		T89	3
auto[0]	auto[1]	valid[0]	auto[0]	115	1			T13	1		T21	1		T45	1
auto[0]	auto[1]	valid[0]	auto[1]	138	1			T17	4		T87	6		T88	2
auto[0]	auto[1]	valid[1]	auto[0]	138	1			T13	1		T18	1		T21	1
auto[0]	auto[1]	valid[1]	auto[1]	154	1			T17	3		T87	5		T88	1
auto[0]	auto[1]	valid[2]	auto[0]	124	1			T10	1		T13	2		T21	1
auto[0]	auto[1]	valid[2]	auto[1]	129	1			T87	1		T89	2		T172	1
auto[0]	auto[1]	valid[3]	auto[0]	125	1			T20	1		T21	2		T86	2
auto[0]	auto[1]	valid[3]	auto[1]	151	1			T17	5		T87	4		T88	1
auto[0]	auto[1]	valid[4]	auto[0]	147	1			T18	1		T21	1		T46	2
auto[0]	auto[1]	valid[4]	auto[1]	137	1			T13	1		T17	4		T46	1
auto[1]	auto[0]	valid[0]	auto[0]	68	1			T13	1		T62	1		T30	1
auto[1]	auto[0]	valid[1]	auto[0]	83	1			T18	1		T45	1		T46	2
auto[1]	auto[0]	valid[2]	auto[0]	64	1			T20	1		T21	1		T43	1
auto[1]	auto[0]	valid[3]	auto[0]	75	1			T13	1		T21	1		T46	1
auto[1]	auto[0]	valid[4]	auto[0]	79	1			T13	1		T21	1		T330	1
auto[1]	auto[1]	valid[0]	auto[0]	75	1			T28	1		T172	1		T326	1
auto[1]	auto[1]	valid[1]	auto[0]	64	1			T43	1		T62	1		T30	2
auto[1]	auto[1]	valid[2]	auto[0]	69	1			T13	1		T18	1		T21	3
auto[1]	auto[1]	valid[3]	auto[0]	78	1			T13	1		T21	2		T25	1
auto[1]	auto[1]	valid[4]	auto[0]	77	1			T13	1		T21	1		T62	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal