Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49986

1

T8

3

T10

79

T13

320

auto[1]

15536

1

T13

57

T17

299

T25

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47497

1

T8

2

T10

49

T13

245

auto[1]

18025

1

T8

1

T10

30

T13

132

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33840	1			T8	2		T10	38		T13	192
others[1]	5497	1			T8	1		T10	8		T13	29
others[2]	5531	1			T10	8		T13	29		T14	3
others[3]	6209	1			T10	8		T13	34		T14	3
interest[1]	3677	1			T10	4		T13	16		T14	1
interest[4]	22091	1			T8	1		T10	26		T13	126
interest[64]	10768	1			T10	13		T13	77		T14	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16342	1			T8	2		T10	21		T13	106
auto[0]	auto[0]	others[1]	2686	1			T10	5		T13	15		T14	2
auto[0]	auto[0]	others[2]	2736	1			T10	5		T13	12		T14	3
auto[0]	auto[0]	others[3]	3072	1			T10	7		T13	14		T14	3
auto[0]	auto[0]	interest[1]	1787	1			T10	4		T13	6		T14	1
auto[0]	auto[0]	interest[4]	10682	1			T8	1		T10	13		T13	67
auto[0]	auto[0]	interest[64]	5338	1			T10	7		T13	35		T14	3
auto[0]	auto[1]	others[0]	8245	1			T13	27		T17	152		T25	4
auto[0]	auto[1]	others[1]	1305	1			T13	4		T17	24		T25	1
auto[0]	auto[1]	others[2]	1270	1			T13	4		T17	29		T43	2
auto[0]	auto[1]	others[3]	1437	1			T13	6		T17	23		T25	2
auto[0]	auto[1]	interest[1]	889	1			T13	1		T17	17		T43	2
auto[0]	auto[1]	interest[4]	5508	1			T13	18		T17	95		T25	2
auto[0]	auto[1]	interest[64]	2390	1			T13	15		T17	54		T43	8
auto[1]	auto[0]	others[0]	9253	1			T10	17		T13	59		T14	4
auto[1]	auto[0]	others[1]	1506	1			T8	1		T10	3		T13	10
auto[1]	auto[0]	others[2]	1525	1			T10	3		T13	13		T18	7
auto[1]	auto[0]	others[3]	1700	1			T10	1		T13	14		T18	5
auto[1]	auto[0]	interest[1]	1001	1			T13	9		T18	3		T21	8
auto[1]	auto[0]	interest[4]	5901	1			T10	13		T13	41		T14	2
auto[1]	auto[0]	interest[64]	3040	1			T10	6		T13	27		T18	9

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal