Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	864	1			T2	21		T14	4		T62	17
all_values[1]	864	1			T2	21		T14	4		T62	17
all_values[2]	864	1			T2	21		T14	4		T62	17
all_values[3]	864	1			T2	21		T14	4		T62	17
all_values[4]	864	1			T2	21		T14	4		T62	17
all_values[5]	864	1			T2	21		T14	4		T62	17
all_values[6]	864	1			T2	21		T14	4		T62	17
all_values[7]	864	1			T2	21		T14	4		T62	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3598

1

T2

84

T14

17

T62

54

auto[1]

3314

1

T2

84

T14

15

T62

82

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2749

1

T2

64

T14

18

T62

55

auto[1]

4163

1

T2

104

T14

14

T62

81

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3917

1

T2

91

T14

22

T62

77

auto[1]

2995

1

T2

77

T14

10

T62

59

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	195	1			T2	4		T14	1		T62	6
all_values[0]	auto[0]	auto[0]	auto[1]	76	1			T2	2		T14	1		T63	1
all_values[0]	auto[0]	auto[1]	auto[0]	169	1			T2	5		T14	1		T62	5
all_values[0]	auto[0]	auto[1]	auto[1]	71	1			T2	1		T62	2		T63	1
all_values[0]	auto[1]	auto[0]	auto[1]	179	1			T2	6		T62	3		T63	4
all_values[0]	auto[1]	auto[1]	auto[1]	174	1			T2	3		T14	1		T62	1
all_values[1]	auto[0]	auto[0]	auto[0]	169	1			T2	5		T14	1		T62	5
all_values[1]	auto[0]	auto[0]	auto[1]	88	1			T2	1		T172	1		T32	1
all_values[1]	auto[0]	auto[1]	auto[0]	172	1			T2	2		T62	7		T63	2
all_values[1]	auto[0]	auto[1]	auto[1]	83	1			T2	4		T14	1		T63	2
all_values[1]	auto[1]	auto[0]	auto[1]	197	1			T2	2		T62	1		T63	4
all_values[1]	auto[1]	auto[1]	auto[1]	155	1			T2	7		T14	2		T62	4
all_values[2]	auto[0]	auto[0]	auto[0]	172	1			T2	6		T14	1		T62	3
all_values[2]	auto[0]	auto[0]	auto[1]	75	1			T2	1		T62	2		T63	1
all_values[2]	auto[0]	auto[1]	auto[0]	154	1			T2	2		T14	3		T62	4
all_values[2]	auto[0]	auto[1]	auto[1]	84	1			T2	2		T62	2		T30	3
all_values[2]	auto[1]	auto[0]	auto[1]	194	1			T2	4		T62	4		T63	3
all_values[2]	auto[1]	auto[1]	auto[1]	185	1			T2	6		T62	2		T63	3
all_values[3]	auto[0]	auto[0]	auto[0]	155	1			T2	3		T62	1		T63	3
all_values[3]	auto[0]	auto[0]	auto[1]	88	1			T2	2		T62	1		T30	2
all_values[3]	auto[0]	auto[1]	auto[0]	146	1			T2	4		T62	2		T63	2
all_values[3]	auto[0]	auto[1]	auto[1]	102	1			T2	2		T14	2		T62	5
all_values[3]	auto[1]	auto[0]	auto[1]	194	1			T2	3		T14	2		T63	1
all_values[3]	auto[1]	auto[1]	auto[1]	179	1			T2	7		T62	8		T63	3
all_values[4]	auto[0]	auto[0]	auto[0]	178	1			T2	4		T14	2		T62	3
all_values[4]	auto[0]	auto[0]	auto[1]	77	1			T2	4		T30	2		T172	1
all_values[4]	auto[0]	auto[1]	auto[0]	133	1			T2	1		T62	1		T30	1
all_values[4]	auto[0]	auto[1]	auto[1]	101	1			T2	1		T62	2		T63	2
all_values[4]	auto[1]	auto[0]	auto[1]	206	1			T2	9		T14	2		T62	5
all_values[4]	auto[1]	auto[1]	auto[1]	169	1			T2	2		T62	6		T30	4
all_values[5]	auto[0]	auto[0]	auto[0]	207	1			T2	5		T14	2		T62	3
all_values[5]	auto[0]	auto[1]	auto[0]	244	1			T2	8		T14	1		T62	4
all_values[5]	auto[1]	auto[0]	auto[1]	212	1			T2	3		T14	1		T62	4
all_values[5]	auto[1]	auto[1]	auto[1]	201	1			T2	5		T62	6		T30	2
all_values[6]	auto[0]	auto[0]	auto[0]	202	1			T2	2		T14	2		T62	2
all_values[6]	auto[0]	auto[0]	auto[1]	72	1			T2	4		T62	2		T63	1
all_values[6]	auto[0]	auto[1]	auto[0]	143	1			T14	2		T62	4		T63	2
all_values[6]	auto[0]	auto[1]	auto[1]	83	1			T2	2		T63	1		T30	1
all_values[6]	auto[1]	auto[0]	auto[1]	193	1			T2	8		T62	2		T63	2
all_values[6]	auto[1]	auto[1]	auto[1]	171	1			T2	5		T62	7		T63	2
all_values[7]	auto[0]	auto[0]	auto[0]	171	1			T2	5		T14	1		T62	4
all_values[7]	auto[0]	auto[0]	auto[1]	85	1			T62	1		T63	2		T30	2
all_values[7]	auto[0]	auto[1]	auto[0]	139	1			T2	8		T14	1		T62	1
all_values[7]	auto[0]	auto[1]	auto[1]	83	1			T2	1		T62	5		T30	1
all_values[7]	auto[1]	auto[0]	auto[1]	213	1			T2	1		T14	1		T62	2
all_values[7]	auto[1]	auto[1]	auto[1]	173	1			T2	6		T14	1		T62	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal