Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3040359	1			T1	1		T2	1		T3	1
all_values[1]	3040359	1			T1	1		T2	1		T3	1
all_values[2]	3040359	1			T1	1		T2	1		T3	1
all_values[3]	3040359	1			T1	1		T2	1		T3	1
all_values[4]	3040359	1			T1	1		T2	1		T3	1
all_values[5]	3040359	1			T1	1		T2	1		T3	1
all_values[6]	3040359	1			T1	1		T2	1		T3	1
all_values[7]	3040359	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23964100

1

T1

8

T2

8

T3

8

auto[1]

358772

1

T29

38

T37

4785

T33

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24299150

1

T1

8

T2

8

T3

8

auto[1]

23722

1

T16

5

T11

103

T30

126

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	3026177	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	12156	1			T11	92		T30	116		T44	2
all_values[0]	auto[1]	auto[0]	1741	1			T29	2		T37	2		T33	1
all_values[0]	auto[1]	auto[1]	285	1			T29	2		T37	2		T33	4
all_values[1]	auto[0]	auto[0]	2975210	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	6185	1			T11	11		T30	10		T44	2
all_values[1]	auto[1]	auto[0]	58527	1			T29	5		T37	5		T33	2
all_values[1]	auto[1]	auto[1]	437	1			T29	2		T37	1		T33	1
all_values[2]	auto[0]	auto[0]	2949801	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2383	1			T44	2		T32	62		T40	15
all_values[2]	auto[1]	auto[0]	87985	1			T29	2		T37	2376		T33	4
all_values[2]	auto[1]	auto[1]	190	1			T29	1		T37	1		T33	1
all_values[3]	auto[0]	auto[0]	3014329	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	204	1			T29	2		T148	4		T164	9
all_values[3]	auto[1]	auto[0]	25623	1			T29	3		T37	3		T33	2
all_values[3]	auto[1]	auto[1]	203	1			T29	1		T33	4		T148	3
all_values[4]	auto[0]	auto[0]	3014815	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	211	1			T29	1		T37	4		T148	3
all_values[4]	auto[1]	auto[0]	25137	1			T29	3		T37	6		T33	1
all_values[4]	auto[1]	auto[1]	196	1			T29	5		T37	3		T33	4
all_values[5]	auto[0]	auto[0]	2949869	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	307	1			T16	5		T259	7		T54	5
all_values[5]	auto[1]	auto[0]	90015	1			T29	2		T37	1		T33	3
all_values[5]	auto[1]	auto[1]	168	1			T29	3		T37	2		T33	1
all_values[6]	auto[0]	auto[0]	3005019	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	209	1			T29	5		T37	4		T33	3
all_values[6]	auto[1]	auto[0]	34935	1			T29	1		T37	4		T33	1
all_values[6]	auto[1]	auto[1]	196	1			T37	2		T33	4		T148	5
all_values[7]	auto[0]	auto[0]	3007031	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	194	1			T29	3		T37	3		T148	6
all_values[7]	auto[1]	auto[0]	32936	1			T29	5		T37	2375		T33	2
all_values[7]	auto[1]	auto[1]	198	1			T29	1		T37	2		T33	2