Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	30710	1			T1	4		T2	4		T3	14
auto[SpiFlashAddrCfg]	6537	1			T2	6		T8	2		T9	8
auto[SpiFlashAddr3b]	7832	1			T2	4		T11	72		T13	2
auto[SpiFlashAddr4b]	6523	1			T2	4		T9	2		T12	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28524

1

T1

4

T3

14

T8

4

auto[1]

23078

1

T2

18

T11

168

T14

4

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27256

1

T1

4

T2

12

T3

14

auto[1]

24346

1

T2

6

T8

2

T9

10

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	34611	1			T1	4		T2	4		T3	14
values[1]	878	1			T8	2		T11	11		T13	2
values[2]	1331	1			T11	17		T14	4		T15	4
values[3]	1247	1			T11	4		T15	6		T30	2
values[4]	1288	1			T2	2		T9	2		T11	8
values[5]	1293	1			T11	10		T15	3		T30	13
values[6]	1263	1			T11	9		T30	2		T44	6
values[7]	1303	1			T2	2		T11	10		T15	5
values[8]	8388	1			T2	10		T8	2		T12	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27773

1

T1

4

T2

18

T3

14

auto[1]

23829

1

T12

2

T30

156

T44

289

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

49752

1

T1

4

T2

16

T3

14

write

1850

1

T2

2

T9

2

T11

11

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

17001

1

T1

4

T2

10

T3

14

valids[0x1]

34601

1

T2

8

T8

2

T9

71

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1414	1			T8	2		T11	7		T15	5
internal_process_ops[0x5a]	1328	1			T11	6		T15	1		T30	7
internal_process_ops[0x05]	18718	1			T9	61		T11	169		T15	10
internal_process_ops[0x35]	1369	1			T9	2		T11	11		T15	3
internal_process_ops[0x15]	1414	1			T2	2		T11	7		T15	4
internal_process_ops[0x03]	990	1			T11	14		T15	2		T30	3
internal_process_ops[0x0b]	905	1			T2	2		T9	2		T11	8
internal_process_ops[0x3b]	952	1			T2	2		T8	2		T11	7
internal_process_ops[0x6b]	988	1			T9	2		T11	13		T15	6
internal_process_ops[0xbb]	929	1			T2	2		T12	2		T11	11
internal_process_ops[0xeb]	926	1			T2	2		T11	10		T15	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50683

1

T1

4

T2

16

T3

14

auto[1]

919

1

T2

2

T11

6

T15

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49751

1

T1

4

T2

18

T3

14

auto[1]

1851

1

T9

2

T11

16

T15

1

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9500

1

T1

4

T3

14

T8

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5643

1

T2

2

T11

84

T15

17

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1959

1

T8

2

T9

6

T11

27

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1697

1

T2

6

T11

23

T15

19

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2335

1

T11

34

T13

2

T15

12

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2015

1

T2

4

T11

37

T15

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2024

1

T9

2

T11

20

T13

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1671

1

T2

4

T11

20

T14

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

68

1

T11

2

T35

3

T36

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

44

1

T36

1

T163

1

T41

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

55

1

T11

1

T32

1

T35

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

76

1

T2

2

T11

2

T15

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

72

1

T9

2

T11

1

T167

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

49

1

T11

1

T32

3

T36

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

65

1

T37

1

T38

1

T33

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

66

1

T15

1

T32

5

T35

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

60

1

T36

3

T177

4

T38

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

55

1

T33

2

T174

1

T70

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

59

1

T11

1

T36

2

T38

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

50

1

T35

1

T36

2

T38

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

49

1

T32

2

T123

1

T183

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

48

1

T11

3

T36

1

T37

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

58

1

T35

4

T36

1

T163

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

55

1

T35

1

T38

1

T33

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7758

1

T30

40

T44

106

T29

167

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7292

1

T30

31

T44

73

T29

63

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1237

1

T30

19

T44

12

T29

23

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1170

1

T30

12

T44

13

T29

32

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1574

1

T30

13

T44

23

T29

27

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1454

1

T30

11

T44

19

T29

29

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1231

1

T12

2

T30

11

T44

16

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1192

1

T30

11

T44

17

T29

21

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

77

1

T29

1

T40

5

T255

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

67

1

T30

2

T29

1

T40

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

57

1

T29

1

T45

1

T33

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

73

1

T44

3

T256

1

T122

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

63

1

T30

3

T29

3

T33

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

51

1

T29

2

T40

1

T66

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

56

1

T44

1

T255

1

T256

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

52

1

T30

2

T29

1

T45

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

52

1

T44

1

T29

2

T40

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

60

1

T44

2

T256

1

T122

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

53

1

T44

2

T29

1

T40

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

65

1

T29

2

T45

1

T256

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

42

1

T45

2

T257

1

T258

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

49

1

T30

1

T29

4

T40

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

45

1

T44

1

T255

1

T66

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

59

1

T33

2

T66

6

T257

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3666	1			T1	4		T3	14		T11	68
auto[0]	values[0]	valids[0x1]	13968	1			T2	4		T9	71		T11	238
auto[0]	values[1]	valids[0x1]	470	1			T8	2		T11	11		T13	2
auto[0]	values[2]	valids[0x0]	524	1			T11	10		T14	4		T15	1
auto[0]	values[2]	valids[0x1]	293	1			T11	7		T15	3		T32	3
auto[0]	values[3]	valids[0x0]	521	1			T11	4		T15	2		T32	1
auto[0]	values[3]	valids[0x1]	263	1			T15	4		T169	2		T32	3
auto[0]	values[4]	valids[0x0]	513	1			T9	2		T11	4		T15	5
auto[0]	values[4]	valids[0x1]	260	1			T2	2		T11	4		T32	5
auto[0]	values[5]	valids[0x0]	471	1			T11	8		T15	2		T34	4
auto[0]	values[5]	valids[0x1]	276	1			T11	2		T15	1		T32	2
auto[0]	values[6]	valids[0x0]	534	1			T11	9		T32	1		T56	4
auto[0]	values[6]	valids[0x1]	252	1			T32	2		T35	8		T36	4
auto[0]	values[7]	valids[0x0]	488	1			T2	2		T11	6		T15	5
auto[0]	values[7]	valids[0x1]	273	1			T11	4		T34	4		T32	1
auto[0]	values[8]	valids[0x0]	3089	1			T2	8		T8	2		T11	38
auto[0]	values[8]	valids[0x1]	1912	1			T2	2		T11	24		T15	8
auto[1]	values[0]	valids[0x0]	3347	1			T30	36		T44	31		T29	78
auto[1]	values[0]	valids[0x1]	13630	1			T30	56		T44	159		T29	192
auto[1]	values[1]	valids[0x1]	408	1			T30	3		T44	4		T29	7
auto[1]	values[2]	valids[0x0]	333	1			T30	3		T44	5		T29	7
auto[1]	values[2]	valids[0x1]	181	1			T30	2		T44	3		T40	5
auto[1]	values[3]	valids[0x0]	266	1			T44	2		T29	2		T40	6
auto[1]	values[3]	valids[0x1]	197	1			T30	2		T44	11		T29	6
auto[1]	values[4]	valids[0x0]	290	1			T44	2		T29	1		T40	8
auto[1]	values[4]	valids[0x1]	225	1			T30	1		T44	11		T29	8
auto[1]	values[5]	valids[0x0]	334	1			T30	12		T44	7		T29	10
auto[1]	values[5]	valids[0x1]	212	1			T30	1		T44	2		T29	3
auto[1]	values[6]	valids[0x0]	288	1			T30	2		T44	2		T29	2
auto[1]	values[6]	valids[0x1]	189	1			T44	4		T29	6		T40	5
auto[1]	values[7]	valids[0x0]	313	1			T44	8		T29	10		T40	4
auto[1]	values[7]	valids[0x1]	229	1			T30	2		T44	2		T29	5
auto[1]	values[8]	valids[0x0]	2024	1			T12	2		T30	21		T44	20
auto[1]	values[8]	valids[0x1]	1363	1			T30	15		T44	16		T29	28