Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3107563

1

T1

5184

T2

1

T3

2621

auto[1]

17314

1

T9

59

T11

157

T15

7

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

885871

1

T1

5184

T2

1

T3

2621

auto[1]

2239006

1

T9

4883

T11

15646

T15

3780

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	621452	1			T1	1664		T2	1		T3	350
auto[524288:1048575]	334455	1			T3	4		T8	6		T12	38
auto[1048576:1572863]	351758	1			T1	255		T3	758		T8	2
auto[1572864:2097151]	339229	1			T1	233		T12	1		T11	6
auto[2097152:2621439]	340964	1			T3	9		T12	429		T11	2
auto[2621440:3145727]	403944	1			T1	4		T3	565		T8	2
auto[3145728:3670015]	380290	1			T1	3011		T3	735		T8	672
auto[3670016:4194303]	352785	1			T1	17		T3	200		T12	79

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2257079

1

T1

63

T2

1

T3

96

auto[1]

867798

1

T1

5121

T3

2525

T8

677

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2692728

1

T1

1902

T2

1

T3

2621

auto[1]

432149

1

T1

3282

T11

1899

T15

5

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	196317	1			T1	1664		T2	1		T3	350
auto[0]	auto[0]	auto[0:524287]	auto[1]	366522	1			T9	4826		T11	258		T15	1
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	63528	1			T3	4		T8	6		T12	38
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	222407	1			T11	3688		T30	1		T44	577
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	77957	1			T1	4		T3	758		T8	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	230366	1			T11	5441		T15	1978		T30	768
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	93655	1			T1	233		T12	1		T11	6
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	183170	1			T15	256		T30	4		T44	1669
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	102865	1			T3	9		T12	429		T11	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	202066	1			T15	256		T30	1877		T44	1295
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	126024	1			T1	1		T3	565		T8	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	221275	1			T11	132		T15	256		T30	256
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	134199	1			T3	735		T8	672		T12	286
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	178405	1			T11	644		T15	512		T30	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	79061	1			T3	200		T12	79		T11	11
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	200423	1			T11	3577		T15	512		T44	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	1274	1			T11	2		T44	1		T165	5
auto[0]	auto[1]	auto[0:524287]	auto[1]	54817	1			T11	5		T40	768		T35	2536
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	831	1			T11	2		T15	1		T30	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	46005	1			T29	256		T40	515		T36	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1410	1			T1	251		T11	3		T30	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	40121	1			T36	129		T38	128		T33	772
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	911	1			T30	1		T29	2		T40	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	59518	1			T30	2		T40	1719		T35	3727
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	673	1			T15	1		T30	6		T44	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	33066	1			T15	3		T30	515		T44	513
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	916	1			T1	3		T11	4		T44	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	53509	1			T11	468		T29	129		T32	261
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	3312	1			T1	3011		T11	1		T30	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	61984	1			T11	513		T30	92		T40	260
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1083	1			T1	17		T11	14		T32	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	69893	1			T11	779		T32	2879		T45	128
auto[1]	auto[0]	auto[0:524287]	auto[0]	244	1			T9	2		T11	2		T15	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	1981	1			T9	57		T11	4		T15	6
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	146	1			T11	1		T30	1		T44	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1181	1			T11	21		T30	2		T44	7
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	181	1			T11	3		T44	1		T29	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1555	1			T11	5		T44	27		T29	15
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	179	1			T30	1		T29	6		T32	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1465	1			T30	1		T29	15		T32	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	194	1			T29	3		T40	1		T36	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1599	1			T29	16		T40	4		T36	66
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	201	1			T11	1		T44	1		T32	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1562	1			T11	2		T44	3		T32	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	197	1			T30	1		T29	5		T32	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1840	1			T29	18		T32	5		T45	25
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	198	1			T11	2		T44	1		T29	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1765	1			T11	8		T44	20		T29	7
auto[1]	auto[1]	auto[0:524287]	auto[0]	36	1			T33	3		T256	1		T41	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	261	1			T33	4		T256	12		T41	3
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	41	1			T40	1		T36	1		T37	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	316	1			T40	7		T36	7		T39	28
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	34	1			T36	1		T255	1		T41	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	134	1			T36	17		T255	1		T257	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	30	1			T40	2		T36	1		T33	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	301	1			T40	7		T36	18		T66	32
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	43	1			T30	3		T44	1		T36	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	458	1			T30	1		T44	47		T36	6
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	37	1			T29	1		T38	1		T33	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	420	1			T29	6		T38	5		T33	18
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	43	1			T11	1		T30	2		T33	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	310	1			T11	18		T30	4		T33	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	51	1			T11	6		T32	1		T273	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	311	1			T11	83		T32	5		T184	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1819406	1			T1	7		T2	1		T3	96
auto[0]	auto[0]	auto[1]	858834	1			T1	1895		T3	2525		T8	677
auto[0]	auto[1]	auto[0]	420734	1			T1	56		T11	1786		T15	5
auto[0]	auto[1]	auto[1]	8589	1			T1	3226		T11	5		T165	1
auto[1]	auto[0]	auto[0]	14185	1			T9	59		T11	46		T15	6
auto[1]	auto[0]	auto[1]	303	1			T11	3		T15	1		T30	1
auto[1]	auto[1]	auto[0]	2754	1			T11	107		T30	10		T44	48
auto[1]	auto[1]	auto[1]	72	1			T11	1		T36	2		T39	1