Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16263

1

T1

4

T3

14

T8

4

auto[1]

11510

1

T2

18

T11

168

T14

4

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3334	1			T212	14		T169	2		T166	16
values[1]	3648	1			T2	18		T11	91		T15	40
values[2]	3664	1			T3	14		T11	121		T15	27
values[3]	3096	1			T11	139		T13	4		T14	4
values[4]	3877	1			T9	73		T11	57		T15	20
values[5]	3737	1			T32	69		T35	40		T36	177
values[6]	3154	1			T11	29		T36	151		T37	21
values[7]	3263	1			T1	4		T8	4		T32	43

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4107	1			T14	4		T212	14		T32	24
values[1]	2924	1			T11	42		T15	40		T168	2
values[2]	3458	1			T9	73		T11	45		T38	62
values[3]	3486	1			T1	4		T8	4		T11	25
values[4]	3255	1			T2	18		T11	163		T32	78
values[5]	3281	1			T3	14		T11	57		T165	2
values[6]	3921	1			T11	74		T15	20		T35	20
values[7]	3341	1			T11	31		T15	27		T169	2

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	239	1			T212	14		T166	16		T37	9
auto[0]	values[0]	values[1]	262	1			T35	13		T36	13		T231	11
auto[0]	values[0]	values[2]	289	1			T201	12		T123	9		T173	18
auto[0]	values[0]	values[3]	230	1			T131	11		T291	12		T292	12
auto[0]	values[0]	values[4]	290	1			T205	8		T130	4		T183	35
auto[0]	values[0]	values[5]	297	1			T35	13		T272	12		T70	94
auto[0]	values[0]	values[6]	238	1			T67	55		T217	11		T68	34
auto[0]	values[0]	values[7]	153	1			T169	2		T84	6		T293	13
auto[0]	values[1]	values[0]	426	1			T39	13		T210	4		T174	54
auto[0]	values[1]	values[1]	285	1			T15	10		T38	11		T195	11
auto[0]	values[1]	values[2]	185	1			T11	15		T33	14		T290	12
auto[0]	values[1]	values[3]	383	1			T11	19		T32	5		T35	12
auto[0]	values[1]	values[4]	185	1			T11	14		T163	79		T279	8
auto[0]	values[1]	values[5]	245	1			T33	16		T163	12		T126	13
auto[0]	values[1]	values[6]	276	1			T11	17		T15	7		T163	17
auto[0]	values[1]	values[7]	211	1			T127	8		T184	32		T175	12
auto[0]	values[2]	values[0]	279	1			T32	14		T41	29		T70	27
auto[0]	values[2]	values[1]	322	1			T11	22		T183	22		T184	12
auto[0]	values[2]	values[2]	372	1			T39	12		T41	32		T123	13
auto[0]	values[2]	values[3]	204	1			T218	10		T183	17		T70	11
auto[0]	values[2]	values[4]	145	1			T11	14		T213	4		T175	13
auto[0]	values[2]	values[5]	213	1			T3	14		T33	12		T123	10
auto[0]	values[2]	values[6]	272	1			T11	13		T36	58		T217	14
auto[0]	values[2]	values[7]	241	1			T11	29		T15	10		T159	12
auto[0]	values[3]	values[0]	149	1			T33	11		T163	6		T173	10
auto[0]	values[3]	values[1]	178	1			T37	14		T123	14		T173	11
auto[0]	values[3]	values[2]	153	1			T11	7		T38	10		T173	7
auto[0]	values[3]	values[3]	357	1			T13	4		T200	24		T217	19
auto[0]	values[3]	values[4]	205	1			T11	48		T32	11		T194	2
auto[0]	values[3]	values[5]	157	1			T170	10		T35	13		T41	14
auto[0]	values[3]	values[6]	215	1			T186	26		T217	13		T284	11
auto[0]	values[3]	values[7]	416	1			T163	11		T164	6		T294	14
auto[0]	values[4]	values[0]	392	1			T35	14		T36	9		T191	8
auto[0]	values[4]	values[1]	151	1			T15	8		T35	14		T36	6
auto[0]	values[4]	values[2]	347	1			T9	73		T39	12		T196	20
auto[0]	values[4]	values[3]	263	1			T167	4		T34	20		T36	15
auto[0]	values[4]	values[4]	259	1			T36	78		T189	20		T295	6
auto[0]	values[4]	values[5]	316	1			T11	50		T165	2		T37	30
auto[0]	values[4]	values[6]	336	1			T38	9		T271	65		T174	15
auto[0]	values[4]	values[7]	278	1			T37	15		T217	15		T171	23
auto[0]	values[5]	values[0]	518	1			T177	194		T33	10		T46	13
auto[0]	values[5]	values[1]	117	1			T164	13		T184	12		T24	15
auto[0]	values[5]	values[2]	171	1			T38	13		T175	11		T296	2
auto[0]	values[5]	values[3]	234	1			T163	18		T184	7		T175	10
auto[0]	values[5]	values[4]	331	1			T32	27		T35	12		T36	13
auto[0]	values[5]	values[5]	254	1			T36	39		T128	2		T46	32
auto[0]	values[5]	values[6]	330	1			T174	56		T180	23		T195	11
auto[0]	values[5]	values[7]	252	1			T32	11		T35	13		T37	9
auto[0]	values[6]	values[0]	191	1			T126	12		T70	27		T67	13
auto[0]	values[6]	values[1]	315	1			T36	83		T123	14		T211	9
auto[0]	values[6]	values[2]	378	1			T38	16		T286	32		T41	14
auto[0]	values[6]	values[3]	212	1			T33	21		T46	17		T149	16
auto[0]	values[6]	values[4]	179	1			T37	12		T38	16		T185	8
auto[0]	values[6]	values[5]	180	1			T123	12		T129	2		T149	18
auto[0]	values[6]	values[6]	168	1			T11	21		T241	7		T131	14
auto[0]	values[6]	values[7]	153	1			T36	11		T275	20		T217	11
auto[0]	values[7]	values[0]	214	1			T174	13		T180	8		T70	14
auto[0]	values[7]	values[1]	336	1			T32	11		T215	12		T182	2
auto[0]	values[7]	values[2]	240	1			T123	11		T180	12		T175	8
auto[0]	values[7]	values[3]	138	1			T1	4		T8	4		T175	13
auto[0]	values[7]	values[4]	183	1			T32	11		T163	9		T41	8
auto[0]	values[7]	values[5]	165	1			T35	9		T126	9		T175	12
auto[0]	values[7]	values[6]	299	1			T35	11		T38	13		T163	37
auto[0]	values[7]	values[7]	291	1			T56	20		T174	12		T180	8
auto[1]	values[0]	values[0]	269	1			T37	11		T33	14		T163	6
auto[1]	values[0]	values[1]	131	1			T35	9		T36	7		T231	15
auto[1]	values[0]	values[2]	142	1			T123	11		T173	10		T67	5
auto[1]	values[0]	values[3]	127	1			T131	9		T232	16		T223	18
auto[1]	values[0]	values[4]	117	1			T183	10		T184	25		T207	10
auto[1]	values[0]	values[5]	148	1			T35	11		T70	7		T67	6
auto[1]	values[0]	values[6]	316	1			T67	9		T217	14		T68	5
auto[1]	values[0]	values[7]	86	1			T293	9		T193	4		T24	10
auto[1]	values[1]	values[0]	200	1			T39	37		T174	4		T195	10
auto[1]	values[1]	values[1]	228	1			T15	10		T38	12		T195	10
auto[1]	values[1]	values[2]	100	1			T11	9		T33	6		T173	7
auto[1]	values[1]	values[3]	192	1			T11	6		T32	16		T35	8
auto[1]	values[1]	values[4]	182	1			T2	18		T11	6		T163	3
auto[1]	values[1]	values[5]	161	1			T33	7		T163	8		T126	8
auto[1]	values[1]	values[6]	289	1			T11	5		T15	13		T163	4
auto[1]	values[1]	values[7]	100	1			T184	11		T175	8		T270	9
auto[1]	values[2]	values[0]	230	1			T32	10		T41	10		T70	6
auto[1]	values[2]	values[1]	186	1			T11	20		T168	2		T183	10
auto[1]	values[2]	values[2]	245	1			T39	8		T41	9		T123	49
auto[1]	values[2]	values[3]	318	1			T183	7		T70	31		T67	10
auto[1]	values[2]	values[4]	135	1			T11	11		T175	7		T171	16
auto[1]	values[2]	values[5]	130	1			T33	8		T123	10		T173	7
auto[1]	values[2]	values[6]	233	1			T11	10		T36	98		T217	6
auto[1]	values[2]	values[7]	139	1			T11	2		T15	17		T214	18
auto[1]	values[3]	values[0]	184	1			T14	4		T33	61		T163	14
auto[1]	values[3]	values[1]	72	1			T37	8		T123	6		T173	9
auto[1]	values[3]	values[2]	158	1			T11	14		T38	12		T173	13
auto[1]	values[3]	values[3]	79	1			T217	7		T226	7		T172	12
auto[1]	values[3]	values[4]	148	1			T11	70		T32	10		T195	8
auto[1]	values[3]	values[5]	174	1			T35	8		T41	6		T197	7
auto[1]	values[3]	values[6]	321	1			T217	9		T284	9		T225	8
auto[1]	values[3]	values[7]	130	1			T163	9		T164	24		T67	13
auto[1]	values[4]	values[0]	216	1			T35	6		T36	21		T70	25
auto[1]	values[4]	values[1]	81	1			T15	12		T35	6		T36	32
auto[1]	values[4]	values[2]	136	1			T39	8		T197	12		T225	13
auto[1]	values[4]	values[3]	288	1			T36	5		T180	6		T70	86
auto[1]	values[4]	values[4]	185	1			T36	11		T175	11		T24	19
auto[1]	values[4]	values[5]	198	1			T11	7		T37	13		T184	11
auto[1]	values[4]	values[6]	137	1			T38	11		T174	5		T180	19
auto[1]	values[4]	values[7]	294	1			T37	5		T217	5		T171	20
auto[1]	values[5]	values[0]	214	1			T33	10		T46	9		T297	4
auto[1]	values[5]	values[1]	69	1			T164	8		T184	12		T24	5
auto[1]	values[5]	values[2]	101	1			T38	7		T175	9		T171	2
auto[1]	values[5]	values[3]	183	1			T163	5		T184	13		T175	10
auto[1]	values[5]	values[4]	195	1			T32	10		T35	8		T36	7
auto[1]	values[5]	values[5]	311	1			T36	118		T46	7		T193	12
auto[1]	values[5]	values[6]	188	1			T174	8		T180	17		T195	9
auto[1]	values[5]	values[7]	269	1			T32	21		T35	7		T37	13
auto[1]	values[6]	values[0]	186	1			T126	8		T70	8		T67	36
auto[1]	values[6]	values[1]	126	1			T36	7		T123	8		T211	11
auto[1]	values[6]	values[2]	219	1			T38	4		T41	13		T46	16
auto[1]	values[6]	values[3]	191	1			T33	5		T46	5		T149	4
auto[1]	values[6]	values[4]	179	1			T37	9		T38	10		T70	105
auto[1]	values[6]	values[5]	214	1			T123	8		T149	6		T67	84
auto[1]	values[6]	values[6]	125	1			T11	8		T241	17		T131	6
auto[1]	values[6]	values[7]	138	1			T36	50		T217	10		T175	5
auto[1]	values[7]	values[0]	200	1			T174	7		T180	17		T70	6
auto[1]	values[7]	values[1]	65	1			T32	12		T176	5		T172	8
auto[1]	values[7]	values[2]	222	1			T123	9		T180	8		T175	12
auto[1]	values[7]	values[3]	87	1			T175	7		T241	6		T132	33
auto[1]	values[7]	values[4]	337	1			T32	9		T163	11		T41	27
auto[1]	values[7]	values[5]	118	1			T35	11		T126	11		T175	12
auto[1]	values[7]	values[6]	178	1			T35	9		T38	11		T163	23
auto[1]	values[7]	values[7]	190	1			T174	40		T180	25		T149	11