Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	340	1			T11	3		T15	2		T32	2
auto[ReadAddrCrossIntoMailbox]	291	1			T11	2		T15	3		T32	2
auto[ReadAddrCrossOutOfMailbox]	277	1			T11	4		T15	2		T32	5
auto[ReadAddrCrossAllMailbox]	216	1			T11	2		T15	1		T32	4
auto[ReadAddrOutsideMailbox]	3284	1			T2	8		T8	2		T9	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2186

1

T2

4

T8

1

T9

2

auto[1]

2222

1

T2

4

T8

1

T9

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	766	1			T11	14		T15	2		T169	2
read_ops[0x0b]	691	1			T2	2		T9	2		T11	8
read_ops[0x3b]	714	1			T2	2		T8	2		T11	7
read_ops[0x6b]	781	1			T9	2		T11	13		T15	6
read_ops[0xbb]	728	1			T2	2		T11	11		T15	3
read_ops[0xeb]	728	1			T2	2		T11	10		T15	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T36	1		T70	1		T171	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T11	1		T32	1		T174	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T11	1		T38	1		T163	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T35	1		T123	2		T184	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T36	1		T183	1		T173	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T33	2		T123	1		T217	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T11	1		T123	1		T183	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T32	2		T211	1		T70	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	277	1			T11	7		T169	1		T32	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T11	4		T15	2		T169	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T180	1		T195	1		T70	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T36	2		T173	1		T180	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T183	1		T180	1		T70	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T32	1		T36	1		T173	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T37	1		T173	1		T70	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T11	1		T15	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T32	2		T195	1		T217	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T36	1		T163	2		T180	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	264	1			T2	1		T9	1		T11	4
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	248	1			T2	1		T9	1		T11	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T11	1		T38	1		T39	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T37	1		T33	1		T173	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T166	1		T37	1		T205	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T166	1		T205	2		T46	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T32	1		T38	1		T123	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T36	2		T123	1		T174	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T205	1		T164	1		T149	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T15	1		T205	1		T173	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T2	1		T8	1		T11	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	253	1			T2	1		T8	1		T11	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T11	1		T35	2		T185	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T15	1		T39	1		T185	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T290	1		T195	1		T217	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T15	2		T32	1		T36	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T32	1		T290	1		T173	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T163	1		T290	1		T195	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T36	1		T37	1		T163	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T37	1		T290	1		T180	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	304	1			T9	1		T11	6		T15	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	281	1			T9	1		T11	6		T15	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T211	1		T149	1		T70	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T32	1		T37	1		T38	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T70	1		T184	1		T175	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	11	1			T39	1		T46	1		T224	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T11	2		T163	2		T184	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T15	1		T32	1		T195	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T11	1		T205	1		T180	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T35	1		T38	1		T205	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	256	1			T2	1		T11	4		T34	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	295	1			T2	1		T11	4		T15	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T35	1		T163	1		T174	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T15	1		T183	1		T180	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T11	1		T35	1		T36	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T15	1		T37	1		T290	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T32	2		T166	3		T39	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T11	1		T166	3		T149	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T37	1		T290	1		T174	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T290	1		T70	1		T217	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	244	1			T2	1		T11	1		T15	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	284	1			T2	1		T11	7		T15	1