Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3040359	1			T1	1		T2	1		T3	1
all_pins[1]	3040359	1			T1	1		T2	1		T3	1
all_pins[2]	3040359	1			T1	1		T2	1		T3	1
all_pins[3]	3040359	1			T1	1		T2	1		T3	1
all_pins[4]	3040359	1			T1	1		T2	1		T3	1
all_pins[5]	3040359	1			T1	1		T2	1		T3	1
all_pins[6]	3040359	1			T1	1		T2	1		T3	1
all_pins[7]	3040359	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	24285552	1			T1	8		T2	8		T3	8
values[0x1]	37320	1			T29	15		T37	13		T33	21
transitions[0x0=>0x1]	36599	1			T29	12		T37	12		T33	15
transitions[0x1=>0x0]	36610	1			T29	12		T37	12		T33	15

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3040054	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	305	1			T29	2		T37	2		T33	4
all_pins[0]	transitions[0x0=>0x1]	261	1			T29	2		T37	2		T33	4
all_pins[0]	transitions[0x1=>0x0]	410	1			T29	2		T37	1		T33	1
all_pins[1]	values[0x0]	3039905	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	454	1			T29	2		T37	1		T33	1
all_pins[1]	transitions[0x0=>0x1]	405	1			T29	2		T37	1		T148	4
all_pins[1]	transitions[0x1=>0x0]	145	1			T29	1		T37	1		T148	1
all_pins[2]	values[0x0]	3040165	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	194	1			T29	1		T37	1		T33	1
all_pins[2]	transitions[0x0=>0x1]	144	1			T29	1		T37	1		T164	4
all_pins[2]	transitions[0x1=>0x0]	153	1			T29	1		T33	3		T148	2
all_pins[3]	values[0x0]	3040156	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	203	1			T29	1		T33	4		T148	3
all_pins[3]	transitions[0x0=>0x1]	145	1			T33	2		T148	2		T164	1
all_pins[3]	transitions[0x1=>0x0]	138	1			T29	4		T37	3		T33	2
all_pins[4]	values[0x0]	3040163	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	196	1			T29	5		T37	3		T33	4
all_pins[4]	transitions[0x0=>0x1]	152	1			T29	3		T37	3		T33	4
all_pins[4]	transitions[0x1=>0x0]	877	1			T29	1		T37	2		T33	1
all_pins[5]	values[0x0]	3039438	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	921	1			T29	3		T37	2		T33	1
all_pins[5]	transitions[0x0=>0x1]	544	1			T29	3		T37	2		T163	1
all_pins[5]	transitions[0x1=>0x0]	34472	1			T37	2		T33	3		T148	5
all_pins[6]	values[0x0]	3005510	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	34849	1			T37	2		T33	4		T148	5
all_pins[6]	transitions[0x0=>0x1]	34800	1			T37	2		T33	3		T148	5
all_pins[6]	transitions[0x1=>0x0]	149	1			T29	1		T37	2		T33	1
all_pins[7]	values[0x0]	3040161	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	198	1			T29	1		T37	2		T33	2
all_pins[7]	transitions[0x0=>0x1]	148	1			T29	1		T37	1		T33	2
all_pins[7]	transitions[0x1=>0x0]	266	1			T29	2		T37	1		T33	4