Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	3	125	97.66

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	3	125	97.66	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3807	1			T1	4		T11	75		T165	2
values[1]	3290	1			T2	18		T3	14		T11	20
values[2]	3801	1			T9	73		T11	48		T15	20
values[3]	3046	1			T8	4		T11	22		T35	24
values[4]	3101	1			T11	185		T32	21		T166	16
values[5]	2882	1			T11	20		T15	27		T56	20
values[6]	4100	1			T11	67		T13	4		T14	4
values[7]	3746	1			T167	4		T168	2		T32	75

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3177	1			T11	81		T15	20		T165	2
values[1]	4060	1			T3	14		T11	62		T13	4
values[2]	2931	1			T2	18		T11	98		T36	109
values[3]	4159	1			T15	20		T168	2		T32	37
values[4]	3498	1			T8	4		T11	23		T15	27
values[5]	2522	1			T11	22		T14	4		T169	2
values[6]	3895	1			T9	73		T11	101		T32	32
values[7]	3531	1			T1	4		T11	50		T15	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27330

1

T1

4

T2

16

T3

14

auto[1]

443

1

T2

2

T11

6

T15

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	3	125	97.66	3

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	[values[1]]	0	1	1
[auto[1]]	[values[0]]	[values[5]]	0	1	1
[auto[1]]	[values[7]]	[values[7]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	606	1			T11	24		T165	2		T170	10
auto[0]	values[0]	values[1]	257	1			T70	26		T171	23		T172	20
auto[0]	values[0]	values[2]	558	1			T11	22		T173	20		T46	20
auto[0]	values[0]	values[3]	712	1			T36	107		T174	100		T67	283
auto[0]	values[0]	values[4]	505	1			T39	48		T163	20		T41	22
auto[0]	values[0]	values[5]	172	1			T175	20		T68	34		T69	30
auto[0]	values[0]	values[6]	414	1			T41	38		T173	20		T176	73
auto[0]	values[0]	values[7]	525	1			T1	4		T11	29		T32	24
auto[0]	values[1]	values[0]	354	1			T35	18		T163	22		T70	101
auto[0]	values[1]	values[1]	447	1			T3	14		T11	20		T177	194
auto[0]	values[1]	values[2]	189	1			T2	16		T178	24		T179	2
auto[0]	values[1]	values[3]	303	1			T35	21		T33	19		T174	20
auto[0]	values[1]	values[4]	568	1			T41	35		T180	20		T175	20
auto[0]	values[1]	values[5]	307	1			T169	2		T37	21		T180	20
auto[0]	values[1]	values[6]	594	1			T37	20		T163	20		T181	12
auto[0]	values[1]	values[7]	467	1			T36	37		T173	28		T182	2
auto[0]	values[2]	values[0]	408	1			T15	19		T36	59		T46	24
auto[0]	values[2]	values[1]	557	1			T33	48		T163	20		T183	20
auto[0]	values[2]	values[2]	353	1			T123	82		T70	51		T184	20
auto[0]	values[2]	values[3]	484	1			T32	32		T185	8		T180	20
auto[0]	values[2]	values[4]	510	1			T11	20		T123	36		T174	64
auto[0]	values[2]	values[5]	329	1			T34	20		T36	20		T186	26
auto[0]	values[2]	values[6]	373	1			T9	73		T11	23		T36	28
auto[0]	values[2]	values[7]	715	1			T35	20		T33	23		T163	18
auto[0]	values[3]	values[0]	225	1			T187	6		T175	39		T152	20
auto[0]	values[3]	values[1]	422	1			T127	8		T70	118		T188	22
auto[0]	values[3]	values[2]	510	1			T36	88		T38	20		T189	20
auto[0]	values[3]	values[3]	333	1			T35	23		T190	8		T191	8
auto[0]	values[3]	values[4]	286	1			T8	4		T33	72		T192	10
auto[0]	values[3]	values[5]	345	1			T11	21		T163	20		T123	55
auto[0]	values[3]	values[6]	428	1			T36	59		T46	23		T193	20
auto[0]	values[3]	values[7]	464	1			T36	20		T38	24		T194	2
auto[0]	values[4]	values[0]	427	1			T11	57		T35	20		T37	22
auto[0]	values[4]	values[1]	323	1			T32	21		T195	20		T46	20
auto[0]	values[4]	values[2]	468	1			T11	76		T37	21		T196	20
auto[0]	values[4]	values[3]	430	1			T163	36		T184	34		T197	20
auto[0]	values[4]	values[4]	239	1			T198	4		T46	39		T199	8
auto[0]	values[4]	values[5]	314	1			T200	24		T36	61		T38	19
auto[0]	values[4]	values[6]	608	1			T11	31		T35	19		T36	76
auto[0]	values[4]	values[7]	233	1			T11	21		T166	16		T201	12
auto[0]	values[5]	values[0]	212	1			T37	23		T123	20		T202	10
auto[0]	values[5]	values[1]	625	1			T56	20		T163	28		T123	20
auto[0]	values[5]	values[2]	147	1			T203	12		T204	18		T69	30
auto[0]	values[5]	values[3]	408	1			T36	20		T38	23		T205	8
auto[0]	values[5]	values[4]	307	1			T15	27		T33	19		T70	34
auto[0]	values[5]	values[5]	361	1			T173	21		T206	16		T180	20
auto[0]	values[5]	values[6]	459	1			T11	20		T126	20		T129	2
auto[0]	values[5]	values[7]	314	1			T37	20		T67	44		T207	40
auto[0]	values[6]	values[0]	475	1			T32	21		T39	20		T208	2
auto[0]	values[6]	values[1]	732	1			T11	42		T13	4		T36	93
auto[0]	values[6]	values[2]	285	1			T183	20		T70	20		T209	2
auto[0]	values[6]	values[3]	761	1			T15	18		T35	20		T38	20
auto[0]	values[6]	values[4]	439	1			T210	4		T211	20		T46	22
auto[0]	values[6]	values[5]	354	1			T14	4		T38	23		T126	21
auto[0]	values[6]	values[6]	522	1			T11	25		T180	25		T175	20
auto[0]	values[6]	values[7]	480	1			T15	20		T212	14		T35	20
auto[0]	values[7]	values[0]	419	1			T38	22		T213	4		T174	50
auto[0]	values[7]	values[1]	626	1			T167	4		T37	19		T33	18
auto[0]	values[7]	values[2]	382	1			T36	20		T37	17		T183	24
auto[0]	values[7]	values[3]	657	1			T168	2		T35	21		T41	20
auto[0]	values[7]	values[4]	576	1			T32	40		T214	18		T35	20
auto[0]	values[7]	values[5]	304	1			T215	12		T216	2		T193	20
auto[0]	values[7]	values[6]	431	1			T32	32		T123	20		T217	39
auto[0]	values[7]	values[7]	292	1			T218	10		T184	43		T67	34
auto[1]	values[0]	values[0]	8	1			T219	1		T220	5		T221	2
auto[1]	values[0]	values[2]	11	1			T217	2		T222	2		T223	1
auto[1]	values[0]	values[3]	12	1			T36	3		T174	1		T67	4
auto[1]	values[0]	values[4]	14	1			T39	2		T41	5		T217	1
auto[1]	values[0]	values[6]	6	1			T41	1		T176	1		T224	1
auto[1]	values[0]	values[7]	7	1			T225	4		T226	2		T227	1
auto[1]	values[1]	values[0]	7	1			T35	2		T163	1		T228	1
auto[1]	values[1]	values[1]	10	1			T229	2		T68	1		T230	2
auto[1]	values[1]	values[2]	5	1			T2	2		T132	2		T172	1
auto[1]	values[1]	values[3]	4	1			T33	1		T171	1		T226	2
auto[1]	values[1]	values[4]	9	1			T231	1		T232	3		T233	2
auto[1]	values[1]	values[5]	7	1			T37	1		T226	2		T231	2
auto[1]	values[1]	values[6]	16	1			T152	3		T234	4		T235	1
auto[1]	values[1]	values[7]	3	1			T36	1		T175	1		T193	1
auto[1]	values[2]	values[0]	5	1			T15	1		T46	1		T68	3
auto[1]	values[2]	values[1]	14	1			T33	1		T163	4		T173	2
auto[1]	values[2]	values[2]	4	1			T70	4		-	-		-	-
auto[1]	values[2]	values[3]	15	1			T32	5		T24	1		T228	1
auto[1]	values[2]	values[4]	11	1			T11	3		T195	1		T132	1
auto[1]	values[2]	values[5]	1	1			T68	1		-	-		-	-
auto[1]	values[2]	values[6]	12	1			T11	2		T36	2		T67	1
auto[1]	values[2]	values[7]	10	1			T163	2		T69	1		T236	3
auto[1]	values[3]	values[0]	3	1			T175	1		T69	1		T223	1
auto[1]	values[3]	values[1]	6	1			T24	1		T236	1		T233	2
auto[1]	values[3]	values[2]	5	1			T36	1		T184	1		T171	2
auto[1]	values[3]	values[3]	3	1			T35	1		T176	1		T220	1
auto[1]	values[3]	values[4]	4	1			T171	1		T231	2		T237	1
auto[1]	values[3]	values[5]	3	1			T11	1		T173	1		T228	1
auto[1]	values[3]	values[6]	6	1			T36	1		T132	2		T232	1
auto[1]	values[3]	values[7]	3	1			T38	1		T238	1		T48	1
auto[1]	values[4]	values[0]	12	1			T175	2		T176	1		T152	1
auto[1]	values[4]	values[1]	6	1			T197	1		T228	1		T172	1
auto[1]	values[4]	values[2]	6	1			T70	1		T24	1		T132	2
auto[1]	values[4]	values[3]	7	1			T68	1		T231	1		T237	1
auto[1]	values[4]	values[4]	6	1			T237	2		T239	2		T235	2
auto[1]	values[4]	values[5]	6	1			T38	1		T67	3		T230	1
auto[1]	values[4]	values[6]	14	1			T35	1		T36	2		T231	2
auto[1]	values[4]	values[7]	2	1			T193	2		-	-		-	-
auto[1]	values[5]	values[0]	3	1			T223	2		T240	1		-	-
auto[1]	values[5]	values[1]	10	1			T67	1		T171	1		T225	1
auto[1]	values[5]	values[2]	2	1			T69	1		T234	1		-	-
auto[1]	values[5]	values[3]	8	1			T38	1		T241	1		T132	2
auto[1]	values[5]	values[4]	4	1			T33	1		T224	1		T152	1
auto[1]	values[5]	values[5]	8	1			T149	2		T230	4		T242	2
auto[1]	values[5]	values[6]	4	1			T132	1		T236	2		T243	1
auto[1]	values[5]	values[7]	10	1			T132	1		T244	1		T232	3
auto[1]	values[6]	values[0]	6	1			T230	4		T245	1		T246	1
auto[1]	values[6]	values[1]	6	1			T36	3		T247	1		T248	2
auto[1]	values[6]	values[2]	1	1			T249	1		-	-		-	-
auto[1]	values[6]	values[3]	14	1			T15	2		T211	1		T70	2
auto[1]	values[6]	values[4]	10	1			T250	2		T251	3		T221	2
auto[1]	values[6]	values[5]	6	1			T172	2		T244	1		T233	3
auto[1]	values[6]	values[6]	3	1			T252	1		T250	1		T253	1
auto[1]	values[6]	values[7]	6	1			T175	1		T244	2		T232	1
auto[1]	values[7]	values[0]	7	1			T174	2		T171	1		T176	2
auto[1]	values[7]	values[1]	19	1			T37	1		T33	2		T41	2
auto[1]	values[7]	values[2]	5	1			T37	3		T254	2		-	-
auto[1]	values[7]	values[3]	8	1			T35	1		T164	1		T70	1
auto[1]	values[7]	values[4]	10	1			T32	3		T193	1		T232	1
auto[1]	values[7]	values[5]	5	1			T241	1		T237	4		-	-
auto[1]	values[7]	values[6]	5	1			T217	1		T131	1		T245	1