Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1716

1

T4

3

T10

5

T17

5

auto[1]

1738

1

T4

7

T10

1

T17

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1869

1

T4

10

T10

6

T17

7

auto[1]

1585

1

T17

1

T18

2

T19

11

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2780

1

T4

7

T10

4

T17

3

auto[1]

674

1

T4

3

T10

2

T17

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	726	1			T4	1		T10	2		T17	3
valid[1]	682	1			T4	2		T10	3		T17	1
valid[2]	662	1			T4	1		T17	1		T11	1
valid[3]	705	1			T4	4		T10	1		T17	2
valid[4]	679	1			T4	2		T17	1		T11	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	124	1			T10	1		T18	2		T30	1
auto[0]	auto[0]	valid[0]	auto[1]	176	1			T19	1		T20	2		T22	1
auto[0]	auto[0]	valid[1]	auto[0]	125	1			T10	3		T29	2		T37	1
auto[0]	auto[0]	valid[1]	auto[1]	140	1			T19	1		T20	1		T22	2
auto[0]	auto[0]	valid[2]	auto[0]	104	1			T4	1		T11	1		T30	2
auto[0]	auto[0]	valid[2]	auto[1]	141	1			T17	1		T19	1		T22	1
auto[0]	auto[0]	valid[3]	auto[0]	120	1			T17	1		T29	2		T54	1
auto[0]	auto[0]	valid[3]	auto[1]	163	1			T19	2		T20	1		T22	1
auto[0]	auto[0]	valid[4]	auto[0]	137	1			T4	2		T11	1		T18	2
auto[0]	auto[0]	valid[4]	auto[1]	144	1			T19	2		T22	2		T80	2
auto[0]	auto[1]	valid[0]	auto[0]	138	1			T17	1		T18	1		T29	1
auto[0]	auto[1]	valid[0]	auto[1]	163	1			T19	1		T79	2		T76	1
auto[0]	auto[1]	valid[1]	auto[0]	108	1			T30	1		T29	2		T32	2
auto[0]	auto[1]	valid[1]	auto[1]	176	1			T19	1		T20	2		T22	2
auto[0]	auto[1]	valid[2]	auto[0]	123	1			T30	1		T29	3		T77	2
auto[0]	auto[1]	valid[2]	auto[1]	165	1			T18	1		T20	3		T79	1
auto[0]	auto[1]	valid[3]	auto[0]	113	1			T4	4		T11	1		T30	2
auto[0]	auto[1]	valid[3]	auto[1]	165	1			T18	1		T19	1		T20	2
auto[0]	auto[1]	valid[4]	auto[0]	103	1			T18	1		T29	2		T40	1
auto[0]	auto[1]	valid[4]	auto[1]	152	1			T19	1		T20	2		T22	1
auto[1]	auto[0]	valid[0]	auto[0]	76	1			T17	1		T11	1		T30	1
auto[1]	auto[0]	valid[1]	auto[0]	67	1			T18	2		T32	1		T40	1
auto[1]	auto[0]	valid[2]	auto[0]	57	1			T18	1		T30	1		T35	1
auto[1]	auto[0]	valid[3]	auto[0]	71	1			T10	1		T17	1		T11	1
auto[1]	auto[0]	valid[4]	auto[0]	71	1			T17	1		T18	1		T30	3
auto[1]	auto[1]	valid[0]	auto[0]	49	1			T4	1		T10	1		T17	1
auto[1]	auto[1]	valid[1]	auto[0]	66	1			T4	2		T17	1		T29	1
auto[1]	auto[1]	valid[2]	auto[0]	72	1			T29	2		T37	1		T38	1
auto[1]	auto[1]	valid[3]	auto[0]	73	1			T30	3		T29	1		T32	1
auto[1]	auto[1]	valid[4]	auto[0]	72	1			T18	1		T30	1		T29	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal