Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48719

1

T4

239

T10

189

T16

6

auto[1]

16823

1

T10

32

T17

33

T18

58

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47613

1

T4

163

T10

143

T16

4

auto[1]

17929

1

T4

76

T10

78

T16

2

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33821	1			T4	122		T10	118		T16	4
others[1]	5395	1			T4	21		T10	12		T17	21
others[2]	5580	1			T4	18		T10	19		T17	17
others[3]	6296	1			T4	18		T10	26		T16	1
interest[1]	3612	1			T4	12		T10	12		T17	12
interest[4]	22040	1			T4	78		T10	71		T16	2
interest[64]	10838	1			T4	48		T10	34		T16	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15753	1			T4	83		T10	61		T16	2
auto[0]	auto[0]	others[1]	2510	1			T4	16		T10	9		T17	10
auto[0]	auto[0]	others[2]	2614	1			T4	14		T10	12		T17	10
auto[0]	auto[0]	others[3]	3039	1			T4	12		T10	7		T16	1
auto[0]	auto[0]	interest[1]	1760	1			T4	10		T10	7		T17	6
auto[0]	auto[0]	interest[4]	10250	1			T4	50		T10	37		T17	33
auto[0]	auto[0]	interest[64]	5114	1			T4	28		T10	15		T16	1
auto[0]	auto[1]	others[0]	8840	1			T10	19		T17	16		T18	33
auto[0]	auto[1]	others[1]	1440	1			T17	1		T18	7		T76	8
auto[0]	auto[1]	others[2]	1393	1			T10	3		T17	3		T18	5
auto[0]	auto[1]	others[3]	1590	1			T10	8		T17	4		T18	4
auto[0]	auto[1]	interest[1]	856	1			T17	2		T18	1		T76	7
auto[0]	auto[1]	interest[4]	5803	1			T10	10		T17	8		T18	26
auto[0]	auto[1]	interest[64]	2704	1			T10	2		T17	7		T18	8
auto[1]	auto[0]	others[0]	9228	1			T4	39		T10	38		T16	2
auto[1]	auto[0]	others[1]	1445	1			T4	5		T10	3		T17	10
auto[1]	auto[0]	others[2]	1573	1			T4	4		T10	4		T17	4
auto[1]	auto[0]	others[3]	1667	1			T4	6		T10	11		T17	7
auto[1]	auto[0]	interest[1]	996	1			T4	2		T10	5		T17	4
auto[1]	auto[0]	interest[4]	5987	1			T4	28		T10	24		T16	2
auto[1]	auto[0]	interest[64]	3020	1			T4	20		T10	17		T17	11

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal