Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	802	1			T29	7		T37	14		T33	7
all_values[1]	802	1			T29	7		T37	14		T33	7
all_values[2]	802	1			T29	7		T37	14		T33	7
all_values[3]	802	1			T29	7		T37	14		T33	7
all_values[4]	802	1			T29	7		T37	14		T33	7
all_values[5]	802	1			T29	7		T37	14		T33	7
all_values[6]	802	1			T29	7		T37	14		T33	7
all_values[7]	802	1			T29	7		T37	14		T33	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3411

1

T29

23

T37

68

T33

22

auto[1]

3005

1

T29

33

T37

44

T33

34

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2521

1

T29

17

T37

55

T33

18

auto[1]

3895

1

T29

39

T37

57

T33

38

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3619

1

T29

26

T37

72

T33

28

auto[1]

2797

1

T29

30

T37

40

T33

28

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	165	1			T37	5		T33	1		T148	3
all_values[0]	auto[0]	auto[0]	auto[1]	83	1			T29	2		T37	1		T148	2
all_values[0]	auto[0]	auto[1]	auto[0]	146	1			T37	2		T148	1		T163	1
all_values[0]	auto[0]	auto[1]	auto[1]	78	1			T29	1		T37	2		T33	1
all_values[0]	auto[1]	auto[0]	auto[1]	193	1			T29	1		T37	3		T33	2
all_values[0]	auto[1]	auto[1]	auto[1]	137	1			T29	3		T37	1		T33	3
all_values[1]	auto[0]	auto[0]	auto[0]	154	1			T29	2		T37	1		T33	1
all_values[1]	auto[0]	auto[0]	auto[1]	95	1			T37	3		T33	2		T164	3
all_values[1]	auto[0]	auto[1]	auto[0]	143	1			T29	2		T37	6		T33	3
all_values[1]	auto[0]	auto[1]	auto[1]	70	1			T29	1		T148	1		T163	1
all_values[1]	auto[1]	auto[0]	auto[1]	186	1			T37	4		T148	1		T163	2
all_values[1]	auto[1]	auto[1]	auto[1]	154	1			T29	2		T33	1		T148	5
all_values[2]	auto[0]	auto[0]	auto[0]	169	1			T29	3		T37	2		T148	2
all_values[2]	auto[0]	auto[0]	auto[1]	71	1			T37	1		T33	2		T148	1
all_values[2]	auto[0]	auto[1]	auto[0]	153	1			T29	1		T37	3		T33	2
all_values[2]	auto[0]	auto[1]	auto[1]	71	1			T37	2		T148	1		T164	2
all_values[2]	auto[1]	auto[0]	auto[1]	184	1			T37	4		T148	3		T163	1
all_values[2]	auto[1]	auto[1]	auto[1]	154	1			T29	3		T37	2		T33	3
all_values[3]	auto[0]	auto[0]	auto[0]	155	1			T29	1		T37	10		T33	2
all_values[3]	auto[0]	auto[0]	auto[1]	70	1			T29	1		T148	1		T164	3
all_values[3]	auto[0]	auto[1]	auto[0]	129	1			T29	2		T37	2		T148	3
all_values[3]	auto[0]	auto[1]	auto[1]	86	1			T33	1		T148	1		T149	4
all_values[3]	auto[1]	auto[0]	auto[1]	192	1			T148	5		T163	1		T164	7
all_values[3]	auto[1]	auto[1]	auto[1]	170	1			T29	3		T37	2		T33	4
all_values[4]	auto[0]	auto[0]	auto[0]	133	1			T37	1		T33	2		T148	5
all_values[4]	auto[0]	auto[0]	auto[1]	74	1			T37	2		T148	2		T163	2
all_values[4]	auto[0]	auto[1]	auto[0]	135	1			T37	4		T148	3		T164	5
all_values[4]	auto[0]	auto[1]	auto[1]	74	1			T29	2		T37	1		T33	2
all_values[4]	auto[1]	auto[0]	auto[1]	219	1			T29	2		T37	2		T148	3
all_values[4]	auto[1]	auto[1]	auto[1]	167	1			T29	3		T37	4		T33	3
all_values[5]	auto[0]	auto[0]	auto[0]	242	1			T29	1		T37	6		T33	1
all_values[5]	auto[0]	auto[1]	auto[0]	223	1			T29	3		T37	1		T33	2
all_values[5]	auto[1]	auto[0]	auto[1]	174	1			T37	3		T33	3		T148	4
all_values[5]	auto[1]	auto[1]	auto[1]	163	1			T29	3		T37	4		T33	1
all_values[6]	auto[0]	auto[0]	auto[0]	160	1			T29	1		T37	3		T163	1
all_values[6]	auto[0]	auto[0]	auto[1]	80	1			T29	1		T37	2		T33	1
all_values[6]	auto[0]	auto[1]	auto[0]	124	1			T37	1		T148	2		T163	1
all_values[6]	auto[0]	auto[1]	auto[1]	83	1			T37	1		T33	1		T148	2
all_values[6]	auto[1]	auto[0]	auto[1]	196	1			T29	4		T37	6		T33	2
all_values[6]	auto[1]	auto[1]	auto[1]	159	1			T29	1		T37	1		T33	3
all_values[7]	auto[0]	auto[0]	auto[0]	148	1			T37	3		T33	2		T148	2
all_values[7]	auto[0]	auto[0]	auto[1]	84	1			T29	1		T37	2		T148	3
all_values[7]	auto[0]	auto[1]	auto[0]	142	1			T29	1		T37	5		T33	2
all_values[7]	auto[0]	auto[1]	auto[1]	79	1			T148	1		T164	2		T149	3
all_values[7]	auto[1]	auto[0]	auto[1]	184	1			T29	3		T37	4		T33	1
all_values[7]	auto[1]	auto[1]	auto[1]	165	1			T29	2		T33	2		T148	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal