Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2674899	1			T1	1		T2	1044		T3	1
all_values[1]	2674899	1			T1	1		T2	1044		T3	1
all_values[2]	2674899	1			T1	1		T2	1044		T3	1
all_values[3]	2674899	1			T1	1		T2	1044		T3	1
all_values[4]	2674899	1			T1	1		T2	1044		T3	1
all_values[5]	2674899	1			T1	1		T2	1044		T3	1
all_values[6]	2674899	1			T1	1		T2	1044		T3	1
all_values[7]	2674899	1			T1	1		T2	1044		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21126392

1

T1

8

T2

8352

T3

8

auto[1]

272800

1

T16

74

T35

17

T72

75

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21376704

1

T1

8

T2

8352

T3

8

auto[1]

22488

1

T12

52

T27

2

T15

24

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2634986	1			T1	1		T2	1044		T3	1
all_values[0]	auto[0]	auto[1]	10833	1			T12	52		T27	1		T15	19
all_values[0]	auto[1]	auto[0]	28506	1			T16	7		T35	1		T72	2
all_values[0]	auto[1]	auto[1]	574	1			T16	3		T73	2		T170	4
all_values[1]	auto[0]	auto[0]	2647726	1			T1	1		T2	1044		T3	1
all_values[1]	auto[0]	auto[1]	5687	1			T27	1		T15	5		T16	66
all_values[1]	auto[1]	auto[0]	21057	1			T16	8		T35	1		T72	8
all_values[1]	auto[1]	auto[1]	429	1			T16	4		T35	2		T72	4
all_values[2]	auto[0]	auto[0]	2636590	1			T1	1		T2	1044		T3	1
all_values[2]	auto[0]	auto[1]	2501	1			T16	13		T32	13		T35	31
all_values[2]	auto[1]	auto[0]	35484	1			T16	7		T72	6		T73	25648
all_values[2]	auto[1]	auto[1]	324	1			T16	2		T72	2		T73	96
all_values[3]	auto[0]	auto[0]	2647420	1			T1	1		T2	1044		T3	1
all_values[3]	auto[0]	auto[1]	194	1			T16	2		T72	4		T73	4
all_values[3]	auto[1]	auto[0]	27081	1			T16	5		T35	1		T72	7
all_values[3]	auto[1]	auto[1]	204	1			T16	5		T35	1		T72	2
all_values[4]	auto[0]	auto[0]	2627575	1			T1	1		T2	1044		T3	1
all_values[4]	auto[0]	auto[1]	188	1			T16	3		T35	1		T72	3
all_values[4]	auto[1]	auto[0]	46948	1			T16	6		T35	1		T72	8
all_values[4]	auto[1]	auto[1]	188	1			T16	1		T35	2		T72	4
all_values[5]	auto[0]	auto[0]	2630972	1			T1	1		T2	1044		T3	1
all_values[5]	auto[0]	auto[1]	347	1			T16	6		T17	3		T269	2
all_values[5]	auto[1]	auto[0]	43373	1			T16	3		T35	4		T72	6
all_values[5]	auto[1]	auto[1]	207	1			T16	6		T35	1		T72	4
all_values[6]	auto[0]	auto[0]	2654179	1			T1	1		T2	1044		T3	1
all_values[6]	auto[0]	auto[1]	235	1			T16	6		T35	1		T72	2
all_values[6]	auto[1]	auto[0]	20290	1			T16	6		T35	1		T72	6
all_values[6]	auto[1]	auto[1]	195	1			T16	2		T35	2		T72	5
all_values[7]	auto[0]	auto[0]	2626751	1			T1	1		T2	1044		T3	1
all_values[7]	auto[0]	auto[1]	208	1			T16	2		T35	3		T72	4
all_values[7]	auto[1]	auto[0]	47766	1			T16	7		T72	6		T73	25735
all_values[7]	auto[1]	auto[1]	174	1			T16	2		T72	5		T73	7